Require little-endian host
[riscv-isa-sim.git] / riscv / decode.h
2010-11-22 Andrew Waterman[opcodes, pk, sim, xcc] Tweaked FP encoding
2010-11-22 Andrew Waterman[xcc, sim, pk, opcodes] new instruction encoding!
2010-11-22 Andrew Waterman[opcodes, pk, sim, xcc] made jumps shorter and PC-relative
2010-10-26 Andrew Waterman[sim,xcc,pk,opcodes] static rounding modes for FP insns
2010-10-16 Andrew Waterman[pk, sim] added FPU emulation support to proxy kernel
2010-10-12 Andrew Waterman[sim] added writeback tracing
2010-10-06 Andrew Waterman[xcc] removed CEXC field from FSR
2010-09-23 Andrew Waterman[xcc, sim] eliminated zero-extended immediates
2010-09-21 Andrew Waterman[xcc, sim] changed instruction format so imm12 subs...
2010-09-13 Andrew Waterman[xcc, sim] moved shamt field and renamed shifts
2010-09-13 Andrew Waterman[xcc, sim] branches now are next-PC-based, not PC-based
2010-09-11 Andrew Waterman[sim, pk] cleaned up exception vectors and FP exc flags
2010-09-09 Andrew WatermanMerge branch 'master' of /project/eecs/parlab/git/proje...
2010-09-09 Andrew Waterman[pk, sim] added interrupt support to sim; added timer...
2010-09-07 Andrew Waterman[sim, xcc] branches now have 2-byte-aligned displacements
2010-08-18 Andrew Waterman[sim] integrated SoftFloat-3 with ISA sim; removed...
2010-08-10 Andrew Waterman[xcc,sim] implement FP using softfloat
2010-08-06 Andrew Waterman[sim,xcc] Added first few Hauser FP insns (sign-injection)
2010-08-05 Andrew Waterman[xcc,pk,sim] Added first part of FP support
2010-07-29 Andrew Waterman[sim,xcc] Changed instruction format to RISC-V
2010-07-19 Andrew WatermanReorganized directory structure