projects / riscv-isa-sim.git / history
| 2015-01-03 | Andrew Waterman | On misaligned fetch, set EPC to target, not branch... | blob | commitdiff | raw |
| 2013-09-27 | Andrew Waterman | Use WRITE_RD/WRITE_FRD macros to write registers | blob | commitdiff | raw | diff to current |
| 2013-09-10 | Andrew Waterman | Add rd field to JAL; drop J | blob | commitdiff | raw | diff to current |
| 2011-06-20 | Andrew Waterman | temporary undoing of renaming | blob | commitdiff | raw | diff to current |
| 2011-06-13 | Andrew Waterman | [sim] renamed to riscv-isa-run | blob | commitdiff | raw |
| 2011-06-11 | Andrew Waterman | [xcc] instructions now set PC explicitly | blob | commitdiff | raw | diff to current |
| 2010-12-27 | Andrew Waterman | [sim] cleaned up handling of link register | blob | commitdiff | raw | diff to current |
| 2010-11-22 | Andrew Waterman | [xcc, sim, pk] link register is now x1 | blob | commitdiff | raw | diff to current |
| 2010-07-19 | Andrew Waterman | Reorganized directory structure | blob | commitdiff | raw | diff to current |