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[xcc, sim] changed instruction format so imm12 subs for rs2
[riscv-isa-sim.git]
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riscv
/
insns
/
mffh_d.h
2010-09-21
Andrew Waterman
[xcc, sim] changed instruction format so imm12 subs...
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2010-09-11
Andrew Waterman
[sim, xcc] Added mffh.d/mtflh.d; fixed FP ABI for 32-bit
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2010-09-11
Yunsup Lee
[opcodes,xcc,sim] mffh.d,mtfh.d added (broken commit)
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projects / riscv-isa-sim.git / history