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Added commit logging (--enable-commitlog). Also fixed disasm bug.
[riscv-isa-sim.git]
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riscv
/
rocc.cc
2013-09-27
Andrew Waterman
Use WRITE_RD/WRITE_FRD macros to write registers
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2013-08-13
Andrew Waterman
Implement RoCC and add a dummy RoCC
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