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[riscv-isa-sim.git] / riscv / sv_reg.h
2018-10-30 Luke Kenneth Casso... set elwidth (carry through) from MMU
2018-10-29 Luke Kenneth Casso... add explicit get of data inside sv_freg_t, float32_t...
2018-10-29 Luke Kenneth Casso... add redirector operators for sv_freg_t to uint32 and...
2018-10-27 Luke Kenneth Casso... redirect float128_t through sv_float128_t class instead...
2018-10-27 Luke Kenneth Casso... replace sv_float64_t typedef with class derived from...
2018-10-27 Luke Kenneth Casso... add sv_float32_t override, use explicit float32_t typec...
2018-10-27 Luke Kenneth Casso... replace freg_t typedef with actual sv_freg_t class...
2018-10-26 Luke Kenneth Casso... forgot to mask off data being written within element
2018-10-26 Luke Kenneth Casso... add max elwidth resolver on add operation
2018-10-26 Luke Kenneth Casso... add to_elwidth function, not complete: needs to use...
2018-10-24 Luke Kenneth Casso... make common function for getting bitwidth
2018-10-20 Luke Kenneth Casso... shuffle to calculate actual bitwidth
2018-10-20 Luke Kenneth Casso... make sv_regbase_t public
2018-10-20 Luke Kenneth Casso... add sign-extension bitwidth macros
2018-10-19 Luke Kenneth Casso... split out sv_reg_t elwidth into separate base class
2018-10-19 Luke Kenneth Casso... fixed memory corruption due to use of auto on load_uint...
2018-10-19 Luke Kenneth Casso... temporarily comment out setting of elwidth
2018-10-19 Luke Kenneth Casso... clean up sv_reg_t class
2018-10-19 Luke Kenneth Casso... use class-based sv_reg_t and sv_sreg_t
2018-10-19 Luke Kenneth Casso... bring in new version of sv_reg.h
2018-10-14 Luke Kenneth Casso... bit of a mess: attempted to create a complete arithmeti...
2018-10-13 Luke Kenneth Casso... add sv_reg_t