projects
/
riscv-isa-sim.git
/ history
commit
grep
author
committer
pickaxe
?
search:
re
summary
|
shortlog
|
log
|
commit
|
commitdiff
|
tree
first ⋅ prev ⋅ next
Only break out of the simulator loop on WFI, not on CSR writes
[riscv-isa-sim.git]
/
riscv
/
tracer.h
2015-09-08
Andrew Waterman
Add facility to instrument specific opcodes
blob
|
commitdiff
|
raw
projects / riscv-isa-sim.git / history