Adjust PortInterface traces according to MMU option
[soc.git] / src / soc / simple / test / test_runner.py
2021-08-16 Cesar StraussAdjust PortInterface traces according to MMU option
2021-08-01 Jonathan Neuschäfersoc.simple.test: Rename setup_test_memory to avoid...
2021-07-15 Luke Kenneth Casso... update TestRunner, SVSTATE is now a class that inherits...
2021-07-14 Luke Kenneth Casso... update SVSTATE to 64 bit length (fortunately very easy)
2021-07-12 Luke Kenneth Casso... use standard create_pdecode in TestRunner
2021-07-11 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org...
2021-07-10 Cesar StraussShow some usage of PortInterface in action
2021-05-22 Cesar StraussMove the reset code outside of the sub-test
2021-05-07 Luke Kenneth Casso... how we managed to get this far without noticing that...
2021-05-01 Luke Kenneth Casso... send a DMI RESET at the end of the test.
2021-04-30 Luke Kenneth Casso... add a TestSRAM variant of LoadStore1, for being able...
2021-04-30 Luke Kenneth Casso... add basic test_issuer_mmu.py
2021-04-30 Luke Kenneth Casso... add option to use new mmu_cache_wb ConfigMemoryPortInte...
2021-04-23 Luke Kenneth Casso... move over to from openpower imports
2021-04-03 Cesar StraussAllow the Simulator to handle back-to-back signaling...
2021-03-30 Alain D D WilliamsMerge branch 'master' of git.libre-soc.org:soc
2021-03-30 Luke Kenneth Casso... use port name for INT regfile to match up with test_run...
2021-03-30 Cesar StraussMemory port seems to have been renamed
2021-03-28 Luke Kenneth Casso... rather invasive reduction of SPR regfile size
2021-03-28 Luke Kenneth Casso... reduce number of regfile ports
2021-03-22 Cesar StraussAdd traces for the new FSM and integer predicate decoding
2021-03-09 Cesar StraussAdd some extra debug traces to the GTKWave document
2021-03-09 Cesar StraussCreate a new signal for the Simulator to wait on
2021-03-08 Luke Kenneth Casso... add option in TestRunner to disable svp64 via commandli...
2021-03-03 Luke Kenneth Casso... set SVSTATE in TestRunner using new TestIssuer.svstate_i
2021-03-03 Luke Kenneth Casso... add svstate_i to TestIssuer which mirrors pc_i
2021-02-27 Cesar StraussAdd traces for the new FSM
2021-02-24 Tobias Platentest_runner.py: add needed imports
2021-02-21 Cesar StraussHide the register augmentation traces by default
2021-02-20 Luke Kenneth Casso... whoops set ROM to none by mistake
2021-02-20 Luke Kenneth Casso... remove massive code-duplication, move simple "self...
2021-02-17 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org...
2021-02-17 Tobias Platenadd wishbone signals to gtkwave output
2021-02-17 Cesar StraussAdd the SVSTATE traces to GTKWave to allow debugging...
2021-02-17 Cesar StraussInitialize the core SVSTATE from the corresponding...
2021-02-17 Cesar StraussRevert "Setup SVSTATE, from the test settings, at the...
2021-02-17 Cesar StraussAdd traces to debug SVP64 prefix decoding issues
2021-02-17 Cesar StraussSetup SVSTATE, from the test settings, at the start
2021-02-16 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org...
2021-02-15 Tobias Platentest case for MMU SPRs: PID and PRTBL
2021-02-15 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org...
2021-02-14 Cesar StraussShow traces for the register numbers of the current...
2021-02-14 Luke Kenneth Casso... add TestRunner comments
2021-02-13 Luke Kenneth Casso... split out TestRunner into separate module