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[soc.git]
/
src
/
soc
/
simulator
/
test_sim.py
2020-06-10
Luke Kenneth Casso...
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2020-06-09
Luke Kenneth Casso...
experimenting with CR/LR/XER etc in qemu
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2020-06-08
Michael Nolan
Add register assertions, fix broken tests
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2020-06-08
Michael Nolan
Restore test_sim.py, begin modifying it for testing...
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2020-05-07
Luke Kenneth Casso...
move unused simulator code out the way
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2020-04-20
Tobias Platen
testcase fo mulli
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2020-04-20
Tobias Platen
testcase for addis
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2020-04-20
Tobias Platen
add with carry cleanup and test case
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2020-04-17
Jacob Lifshay
Merge branch 'master' of ssh://git.libre-riscv.org...
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2020-04-09
Tobias Platen
fix 'Object is not an nMigen signal' error in test_sim.py
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2020-04-06
Jacob Lifshay
Merge branch 'master' of ssh://git.libre-riscv.org...
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2020-04-06
Jacob Lifshay
Merge branch 'fix-tests'
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2020-04-06
Jacob Lifshay
almost all tests work
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2020-03-26
Michael Nolan
Add tests for subfic and neg
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2020-03-26
Michael Nolan
Sub instruction working
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2020-03-25
Michael Nolan
Directly compare simulator with qemu
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2020-03-25
Michael Nolan
Assemble whole program instead of instruction by instru...
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2020-03-23
Michael Nolan
Implement load and store of bytes, halfwords, and words
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2020-03-23
Michael Nolan
Add support for extended/indexed ld/st
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2020-03-23
Michael Nolan
Add memory loads and stores to simulator
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2020-03-23
Michael Nolan
Begin adding backend simulator
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