soc.git
3 years agoexperiment with alternative PID in radix mmu
Luke Kenneth Casson Leighton [Sat, 17 Apr 2021 19:27:39 +0000 (20:27 +0100)]
experiment with alternative PID in radix mmu

3 years agopass in SPRs each time on radix test
Luke Kenneth Casson Leighton [Sat, 17 Apr 2021 19:16:59 +0000 (20:16 +0100)]
pass in SPRs each time on radix test
allows for different tests

3 years agoadd LD/ST radix unit test
Luke Kenneth Casson Leighton [Sat, 17 Apr 2021 19:03:34 +0000 (20:03 +0100)]
add LD/ST radix unit test

3 years agoImplement 1<<r3 directly by a shift
Cesar Strauss [Sat, 17 Apr 2021 18:12:29 +0000 (15:12 -0300)]
Implement 1<<r3 directly by a shift

It generates simpler Yosys graphs.

3 years agoradixmmu: fix my mistake about pgbase size
Tobias Platen [Sat, 17 Apr 2021 17:22:12 +0000 (19:22 +0200)]
radixmmu: fix my mistake about pgbase size

3 years agosubmodule update
Luke Kenneth Casson Leighton [Fri, 16 Apr 2021 22:46:02 +0000 (23:46 +0100)]
submodule update

3 years agojtag utils, send tms before tck
Luke Kenneth Casson Leighton [Fri, 16 Apr 2021 19:49:29 +0000 (20:49 +0100)]
jtag utils, send tms before tck

3 years agopass the "old" value of shift to _new_lookup
Tobias Platen [Fri, 16 Apr 2021 19:26:19 +0000 (21:26 +0200)]
pass the "old" value of shift to _new_lookup

3 years agosigh, new_shift wrong bitwidth
Luke Kenneth Casson Leighton [Fri, 16 Apr 2021 18:03:58 +0000 (19:03 +0100)]
sigh, new_shift wrong bitwidth

3 years agoput mbits back into segment_check (like it is in microwatt)
Luke Kenneth Casson Leighton [Fri, 16 Apr 2021 00:28:29 +0000 (01:28 +0100)]
put mbits back into segment_check (like it is in microwatt)

3 years agoradixmmu cleanup
Luke Kenneth Casson Leighton [Fri, 16 Apr 2021 00:08:51 +0000 (01:08 +0100)]
radixmmu cleanup

3 years agocall addrshift and get_pgtable_addr inside while loop for radixmmu
Luke Kenneth Casson Leighton [Fri, 16 Apr 2021 00:04:07 +0000 (01:04 +0100)]
call addrshift and get_pgtable_addr inside while loop for radixmmu

3 years agocode-cleanup in radixmmu
Luke Kenneth Casson Leighton [Fri, 16 Apr 2021 00:00:01 +0000 (01:00 +0100)]
code-cleanup in radixmmu

3 years agowhitespace and corrections to NLS, RTS1, RTS2
Luke Kenneth Casson Leighton [Thu, 15 Apr 2021 23:21:09 +0000 (00:21 +0100)]
whitespace and corrections to NLS, RTS1, RTS2

3 years agofix radix testcase
Tobias Platen [Thu, 15 Apr 2021 17:05:51 +0000 (19:05 +0200)]
fix radix testcase

3 years agoconcat en_sigs together in JTAG to make sure they are not missed out
Luke Kenneth Casson Leighton [Thu, 15 Apr 2021 15:43:12 +0000 (16:43 +0100)]
concat en_sigs together in JTAG to make sure they are not missed out

3 years agoadd icachemmu option to ISACaller
Luke Kenneth Casson Leighton [Thu, 15 Apr 2021 08:48:37 +0000 (09:48 +0100)]
add icachemmu option to ISACaller

3 years agosubmodule update
Luke Kenneth Casson Leighton [Wed, 14 Apr 2021 19:08:38 +0000 (20:08 +0100)]
submodule update

3 years agowhitespace
Luke Kenneth Casson Leighton [Wed, 14 Apr 2021 19:08:28 +0000 (20:08 +0100)]
whitespace

3 years agosubmodule update
Luke Kenneth Casson Leighton [Tue, 13 Apr 2021 16:04:24 +0000 (17:04 +0100)]
submodule update

3 years agoupdate test_caller_radix.py
Tobias Platen [Wed, 14 Apr 2021 18:22:20 +0000 (20:22 +0200)]
update test_caller_radix.py

3 years agoradixmmu: handle badtree
Tobias Platen [Wed, 14 Apr 2021 18:16:00 +0000 (20:16 +0200)]
radixmmu: handle badtree

3 years agoupdate test case for radix mmu
Tobias Platen [Wed, 14 Apr 2021 17:39:08 +0000 (19:39 +0200)]
update test case for radix mmu

3 years agoradixmmu: error handling
Tobias Platen [Wed, 14 Apr 2021 17:34:13 +0000 (19:34 +0200)]
radixmmu: error handling

3 years agomore fixes for radixmmu.py
Tobias Platen [Tue, 13 Apr 2021 17:21:18 +0000 (19:21 +0200)]
more fixes for radixmmu.py

3 years agofix AttributeError in radixmmu testcase
Tobias Platen [Tue, 13 Apr 2021 16:43:37 +0000 (18:43 +0200)]
fix AttributeError in radixmmu testcase

3 years agoradixmmu.py: cleanup
Tobias Platen [Mon, 12 Apr 2021 17:50:20 +0000 (19:50 +0200)]
radixmmu.py: cleanup

3 years agofix bug in radixmmu.py
Tobias Platen [Sun, 11 Apr 2021 18:48:12 +0000 (20:48 +0200)]
fix bug in radixmmu.py

3 years agoradixmmu: more work on segment check
Tobias Platen [Sun, 11 Apr 2021 06:45:06 +0000 (08:45 +0200)]
radixmmu: more work on segment check

3 years agoImplement 1<<r3 predicate mode
Cesar Strauss [Sat, 10 Apr 2021 20:27:48 +0000 (17:27 -0300)]
Implement 1<<r3 predicate mode

The mask bit selected by r3 is set to one.
A possible optimization would be to do step = r3 directly, but this is only
valid in non-zero mode.
The corresponding test cases now pass.

3 years agoAdd 1<<r3 test cases to TestIssuer
Cesar Strauss [Sat, 10 Apr 2021 19:59:19 +0000 (16:59 -0300)]
Add 1<<r3 test cases to TestIssuer

They fail, since it's not implemented yet.

3 years agoAdd test cases for 1<<r3 predication
Cesar Strauss [Sat, 10 Apr 2021 19:40:09 +0000 (16:40 -0300)]
Add test cases for 1<<r3 predication

3 years agoadd blinken lights assembly (not used yet)
Luke Kenneth Casson Leighton [Fri, 9 Apr 2021 11:40:48 +0000 (12:40 +0100)]
add blinken lights assembly (not used yet)

3 years agotest firmware upload program needed to branch back further in order to loop
Luke Kenneth Casson Leighton [Fri, 9 Apr 2021 00:09:32 +0000 (01:09 +0100)]
test firmware upload program needed to branch back further in order to loop

3 years agosort out pc reset when DMI interface requests reset
Luke Kenneth Casson Leighton [Thu, 8 Apr 2021 23:24:42 +0000 (00:24 +0100)]
sort out pc reset when DMI interface requests reset

3 years agosubmodule update
Luke Kenneth Casson Leighton [Thu, 8 Apr 2021 20:53:31 +0000 (21:53 +0100)]
submodule update

3 years agoargh, wb jtag stall probably is not working
Luke Kenneth Casson Leighton [Thu, 8 Apr 2021 20:53:03 +0000 (21:53 +0100)]
argh, wb jtag stall probably is not working

3 years agoupload over 32-bit JTAG Wishbone
Luke Kenneth Casson Leighton [Thu, 8 Apr 2021 20:38:55 +0000 (21:38 +0100)]
upload over 32-bit JTAG Wishbone

3 years agoshrink JTAG master bus to 32-bit (match with litex)
Luke Kenneth Casson Leighton [Thu, 8 Apr 2021 20:21:09 +0000 (21:21 +0100)]
shrink JTAG master bus to 32-bit (match with litex)

3 years agosubmodule update
Luke Kenneth Casson Leighton [Wed, 7 Apr 2021 19:27:37 +0000 (20:27 +0100)]
submodule update

3 years agoWIP: calculate address of first page table entry
Tobias Platen [Wed, 7 Apr 2021 19:17:35 +0000 (21:17 +0200)]
WIP: calculate address of first page table entry

3 years agoradixmmu: fix segment_check function and its caller
Tobias Platen [Wed, 7 Apr 2021 18:26:54 +0000 (20:26 +0200)]
radixmmu: fix segment_check function and its caller

3 years ago4k SRAM Instance needs write-enable @ 8-bit width
Luke Kenneth Casson Leighton [Tue, 6 Apr 2021 21:07:12 +0000 (22:07 +0100)]
4k SRAM Instance needs write-enable @ 8-bit width

3 years ago8-bit granularity on JTAG wishbone
Luke Kenneth Casson Leighton [Tue, 6 Apr 2021 20:38:04 +0000 (21:38 +0100)]
8-bit granularity on JTAG wishbone

3 years agoremove unneeded code
Luke Kenneth Casson Leighton [Tue, 6 Apr 2021 20:35:12 +0000 (21:35 +0100)]
remove unneeded code

3 years agosoc-cocotb-sim submodule update
Staf Verhaegen [Tue, 6 Apr 2021 18:50:58 +0000 (20:50 +0200)]
soc-cocotb-sim submodule update

3 years agoadd mmu_states.dia
Tobias Platen [Tue, 6 Apr 2021 17:21:14 +0000 (19:21 +0200)]
add mmu_states.dia

3 years agogit submodule update
Luke Kenneth Casson Leighton [Tue, 6 Apr 2021 14:58:36 +0000 (15:58 +0100)]
git submodule update

3 years agoMake the VL loop reentrant in HDL
Cesar Strauss [Tue, 6 Apr 2021 11:31:14 +0000 (08:31 -0300)]
Make the VL loop reentrant in HDL

This is done by shifting-out already used mask bits, at predicate fetch.
The corresponding test case now passes.

3 years agoAdd a HDL test case, where we start at the middle of the VL loop
Cesar Strauss [Tue, 6 Apr 2021 11:26:43 +0000 (08:26 -0300)]
Add a HDL test case, where we start at the middle of the VL loop

It is expected to fail, since the HDL is not reentrant at this moment.

3 years agoStart the test case from a point where the predicate bits are zeros
Cesar Strauss [Tue, 6 Apr 2021 11:18:26 +0000 (08:18 -0300)]
Start the test case from a point where the predicate bits are zeros

Since SVSTATE is user-programmable, src/dst step can really point anywhere,
at instruction start. Although interrupts will always restore src/dest step
pointing to a set mask bit, this is not guaranteed in general.

3 years agolitex submodule update
Luke Kenneth Casson Leighton [Mon, 5 Apr 2021 11:06:31 +0000 (12:06 +0100)]
litex submodule update

3 years agosubmodule update
Luke Kenneth Casson Leighton [Mon, 5 Apr 2021 10:47:10 +0000 (11:47 +0100)]
submodule update

3 years agosoc-cocotb-sim submodule update
Staf Verhaegen [Sun, 4 Apr 2021 16:09:17 +0000 (18:09 +0200)]
soc-cocotb-sim submodule update

3 years agoAdd test case for reentrant VL loop
Cesar Strauss [Sun, 4 Apr 2021 11:59:22 +0000 (08:59 -0300)]
Add test case for reentrant VL loop

We explicitly initialize src/dst step, as if we were returning from an
interrupt.

3 years agoReminder for a possible hardware optimization
Cesar Strauss [Sat, 3 Apr 2021 20:12:30 +0000 (17:12 -0300)]
Reminder for a possible hardware optimization

3 years agoBe more precise when using a one-bit constant
Cesar Strauss [Sat, 3 Apr 2021 20:02:39 +0000 (17:02 -0300)]
Be more precise when using a one-bit constant

3 years agoFix typo
Cesar Strauss [Sat, 3 Apr 2021 19:18:56 +0000 (16:18 -0300)]
Fix typo

3 years agoAdd test case with all mask bits equal to zero
Cesar Strauss [Sat, 3 Apr 2021 19:16:48 +0000 (16:16 -0300)]
Add test case with all mask bits equal to zero

3 years agoAdd a test case for integer single predication
Cesar Strauss [Sat, 3 Apr 2021 19:04:49 +0000 (16:04 -0300)]
Add a test case for integer single predication

3 years agoDisallow unknown encmodes in SVP64 Assembly
Cesar Strauss [Sat, 3 Apr 2021 18:48:50 +0000 (15:48 -0300)]
Disallow unknown encmodes in SVP64 Assembly

3 years agoEnable remaining disabled test cases
Cesar Strauss [Sat, 3 Apr 2021 18:45:39 +0000 (15:45 -0300)]
Enable remaining disabled test cases

They all work, now, after the ISA Caller fixes.

3 years agoAllow the Simulator to handle back-to-back signaling from TestIssuer
Cesar Strauss [Sat, 3 Apr 2021 18:40:31 +0000 (15:40 -0300)]
Allow the Simulator to handle back-to-back signaling from TestIssuer

TestIssuer can signal the end of an instruction and, after skipping mask
bits, signal the end of the VL loop, right on the following cycle.
Since there is no handshake between TestIssuer and Simulator, we need to
remove any wait state that would cause the Simulator to miss the one-clock
pulse.

3 years agoSignal the simulator when completing a VL loop
Cesar Strauss [Sat, 3 Apr 2021 18:21:37 +0000 (15:21 -0300)]
Signal the simulator when completing a VL loop

When we reach the end of the VL loop, by skipping masked bits in the
predicate, we still need to synchronize with the Simulator, even if no
instruction was issued.

3 years agoFix typo
Cesar Strauss [Sat, 3 Apr 2021 11:21:21 +0000 (08:21 -0300)]
Fix typo

3 years agoAdd twin predication test
Cesar Strauss [Sat, 3 Apr 2021 11:07:51 +0000 (08:07 -0300)]
Add twin predication test

Another simulator failure. Seems like the VL loop is still not terminating
properly. Will investigate.

3 years agoEnd VL loop as soon as either src/dst step reaches VL
Cesar Strauss [Fri, 2 Apr 2021 22:26:21 +0000 (19:26 -0300)]
End VL loop as soon as either src/dst step reaches VL

Also, avoid incrementing dststep beyond VL-1

3 years agoFix typo
Cesar Strauss [Fri, 2 Apr 2021 22:20:26 +0000 (19:20 -0300)]
Fix typo

3 years agoAdd VEXPAND test case for the ISA Simulator
Cesar Strauss [Fri, 2 Apr 2021 20:43:15 +0000 (17:43 -0300)]
Add VEXPAND test case for the ISA Simulator

The test currently does not pass, there must be a bug somewhere.
Seems like it is skipping the middle source element, as if it was doing
single-pred.

3 years agoAdd VCOMPRESS test case for the ISA Simulator
Cesar Strauss [Fri, 2 Apr 2021 20:25:13 +0000 (17:25 -0300)]
Add VCOMPRESS test case for the ISA Simulator

3 years agoPut sanity check inside the existing '2Pred' case, and simplify
Cesar Strauss [Fri, 2 Apr 2021 19:58:48 +0000 (16:58 -0300)]
Put sanity check inside the existing '2Pred' case, and simplify

3 years agoEnforce explicit src/dest masks on CR twin-predication
Cesar Strauss [Fri, 2 Apr 2021 19:53:32 +0000 (16:53 -0300)]
Enforce explicit src/dest masks on CR twin-predication

3 years agoDisallow mixing of sm=xx and/or dm=xx with m=xx on twin-pred
Cesar Strauss [Fri, 2 Apr 2021 19:32:33 +0000 (16:32 -0300)]
Disallow mixing of sm=xx and/or dm=xx with m=xx on twin-pred

3 years agoDisallow dm=xx on single predication
Cesar Strauss [Fri, 2 Apr 2021 18:51:46 +0000 (15:51 -0300)]
Disallow dm=xx on single predication

Adjust test cases accordingly.

3 years agoFix typo
Cesar Strauss [Fri, 2 Apr 2021 17:04:20 +0000 (14:04 -0300)]
Fix typo

3 years agoReally enforce sm=xx not being allowed on single-pred
Cesar Strauss [Fri, 2 Apr 2021 15:06:00 +0000 (12:06 -0300)]
Really enforce sm=xx not being allowed on single-pred

Before, using m=xx together with sm=xx would defeat the assertion.

3 years agoKeep mask mode flags separate
Cesar Strauss [Fri, 2 Apr 2021 14:23:31 +0000 (11:23 -0300)]
Keep mask mode flags separate

Before, when m=xx was seen, we couldn't tell whether sm=xx or dm=xx was
also seen. We will need this, later.
Adjust uses accordingly, preserving truth value.

3 years agogit submodule update
Luke Kenneth Casson Leighton [Thu, 1 Apr 2021 22:41:24 +0000 (23:41 +0100)]
git submodule update

3 years agoTWI enabled in JTAG boundary scan
Luke Kenneth Casson Leighton [Thu, 1 Apr 2021 22:14:58 +0000 (23:14 +0100)]
TWI enabled in JTAG boundary scan

3 years agogit submodule update
Luke Kenneth Casson Leighton [Thu, 1 Apr 2021 22:08:10 +0000 (23:08 +0100)]
git submodule update

3 years agoreduce subset of functions to be created in JTAG boundary scan
Luke Kenneth Casson Leighton [Thu, 1 Apr 2021 22:07:53 +0000 (23:07 +0100)]
reduce subset of functions to be created in JTAG boundary scan

3 years agouse OrderedDict to restore exact order from JSON file
Luke Kenneth Casson Leighton [Thu, 1 Apr 2021 22:07:26 +0000 (23:07 +0100)]
use OrderedDict to restore exact order from JSON file

3 years agoadd soc-cocotb-sim submodule
Luke Kenneth Casson Leighton [Thu, 1 Apr 2021 21:46:40 +0000 (22:46 +0100)]
add soc-cocotb-sim submodule

3 years agosubmodule update
Luke Kenneth Casson Leighton [Thu, 1 Apr 2021 15:52:11 +0000 (16:52 +0100)]
submodule update

3 years agolibresoc-litex submodule update
Staf Verhaegen [Thu, 1 Apr 2021 12:56:53 +0000 (14:56 +0200)]
libresoc-litex submodule update

3 years agobug in iverilog, segfaults due to empty case statement
Luke Kenneth Casson Leighton [Thu, 1 Apr 2021 12:17:53 +0000 (13:17 +0100)]
bug in iverilog, segfaults due to empty case statement

3 years agoadd no pll ls180 build
Luke Kenneth Casson Leighton [Thu, 1 Apr 2021 12:10:00 +0000 (13:10 +0100)]
add no pll ls180 build

3 years agolibresoc-litex submodule update
Staf Verhaegen [Thu, 1 Apr 2021 11:51:33 +0000 (13:51 +0200)]
libresoc-litex submodule update

3 years ago_new_lookup: remove unused argument mbits
Tobias Platen [Wed, 31 Mar 2021 19:45:57 +0000 (21:45 +0200)]
_new_lookup: remove unused argument mbits

3 years agoradixmmu: read prtable entry
Tobias Platen [Wed, 31 Mar 2021 18:42:24 +0000 (20:42 +0200)]
radixmmu: read prtable entry

3 years agoradixmmu.py: remove redunant code
Tobias Platen [Wed, 31 Mar 2021 17:35:14 +0000 (19:35 +0200)]
radixmmu.py: remove redunant code

3 years agosubmodule update
Luke Kenneth Casson Leighton [Wed, 31 Mar 2021 13:41:48 +0000 (14:41 +0100)]
submodule update

3 years agoMerge branch 'master' of ssh://git.libre-riscv.org:922/soc
Tobias Platen [Tue, 30 Mar 2021 19:28:16 +0000 (21:28 +0200)]
Merge branch 'master' of ssh://git.libre-riscv.org:922/soc

3 years agomore work on _prtable_lookup and testcase
Tobias Platen [Tue, 30 Mar 2021 19:27:23 +0000 (21:27 +0200)]
more work on _prtable_lookup and testcase

3 years agoadd comments
Luke Kenneth Casson Leighton [Tue, 30 Mar 2021 19:16:12 +0000 (20:16 +0100)]
add comments

3 years agouse PRTBL SPR in RADIXMMU
Luke Kenneth Casson Leighton [Tue, 30 Mar 2021 19:09:34 +0000 (20:09 +0100)]
use PRTBL SPR in RADIXMMU

3 years agoMerge branch 'master' of ssh://git.libre-riscv.org:922/soc
Tobias Platen [Tue, 30 Mar 2021 18:45:52 +0000 (20:45 +0200)]
Merge branch 'master' of ssh://git.libre-riscv.org:922/soc

3 years agocomment about microwatt implementation details
Tobias Platen [Tue, 30 Mar 2021 18:11:00 +0000 (20:11 +0200)]
comment about microwatt implementation details

3 years agosubmodule update
Luke Kenneth Casson Leighton [Tue, 30 Mar 2021 18:10:37 +0000 (19:10 +0100)]
submodule update

3 years agoadd comments, correct load addresses
Luke Kenneth Casson Leighton [Tue, 30 Mar 2021 17:40:32 +0000 (18:40 +0100)]
add comments, correct load addresses