add no pll ls180 build

diff --git a/Makefile b/Makefile
index abb446dd00b02008e36f3412235f37be5194d312..8412997a74c3d17be68fc35c703947a8119dc367 100644 (file)
--- a/Makefile
+++ b/Makefile
@@ -36,6 +36,12 @@ testgpio_run_sim:
        python3 src/soc/litex/florent/sim.py --cpu=libresoc \
                        --variant=standardjtagtestgpio
 
+ls180_verilog_nopll:
+       python3 src/soc/simple/issuer_verilog.py \
+               --debug=jtag --enable-core --disable-pll \
+               --enable-xics --disable-svp64 \
+                       src/soc/litex/florent/libresoc/libresoc.v
+
 ls180_verilog:
        python3 src/soc/simple/issuer_verilog.py \
                --debug=jtag --enable-core --enable-pll \