soc.git
2 years agoenable I-Cache wishbone memory type in issuer_verilog.py if MMU requested
Luke Kenneth Casson Leighton [Tue, 21 Dec 2021 16:32:55 +0000 (16:32 +0000)]
enable I-Cache wishbone memory type in issuer_verilog.py if MMU requested

2 years agowhoops issuer_verilog.py enabling mmu has to pass microwatt_mmu
Luke Kenneth Casson Leighton [Tue, 21 Dec 2021 15:57:37 +0000 (15:57 +0000)]
whoops issuer_verilog.py enabling mmu has to pass microwatt_mmu
option to TestMemPSpec

2 years agofor each unit test case in test_issuer_mmu_data_path.py initialise memory
Luke Kenneth Casson Leighton [Tue, 21 Dec 2021 15:47:39 +0000 (15:47 +0000)]
for each unit test case in test_issuer_mmu_data_path.py initialise memory
to empty

2 years agotest_issuer_mmu_data_path.py needs to use wb_get because of
Luke Kenneth Casson Leighton [Tue, 21 Dec 2021 14:21:06 +0000 (14:21 +0000)]
test_issuer_mmu_data_path.py needs to use wb_get because of
reading from i-cache cannot be done without it

2 years agommu code-comments
Luke Kenneth Casson Leighton [Tue, 21 Dec 2021 12:51:45 +0000 (12:51 +0000)]
mmu code-comments

2 years agocomments
Luke Kenneth Casson Leighton [Tue, 21 Dec 2021 05:07:37 +0000 (05:07 +0000)]
comments

2 years agouse prtbl in proc_tbl_wait in mmu
Luke Kenneth Casson Leighton [Tue, 21 Dec 2021 04:59:48 +0000 (04:59 +0000)]
use prtbl in proc_tbl_wait in mmu

2 years agommu.py comments
Luke Kenneth Casson Leighton [Tue, 21 Dec 2021 04:53:45 +0000 (04:53 +0000)]
mmu.py comments

2 years agoset up DAR correctly in unit tests, added set_ldst_spr() which toggles
Luke Kenneth Casson Leighton [Mon, 20 Dec 2021 23:10:09 +0000 (23:10 +0000)]
set up DAR correctly in unit tests, added set_ldst_spr() which toggles
LoadStore1 input flags in order to store DAR in the unit itself

2 years agounit tests for SPRs when MMU enabled,
Luke Kenneth Casson Leighton [Mon, 20 Dec 2021 19:07:44 +0000 (19:07 +0000)]
unit tests for SPRs when MMU enabled,
start setting DAR, DSISR, PIDR, PRTBL etc

2 years agomore code-comments
Luke Kenneth Casson Leighton [Mon, 20 Dec 2021 15:11:46 +0000 (15:11 +0000)]
more code-comments

2 years agocode-comments in MMU
Luke Kenneth Casson Leighton [Mon, 20 Dec 2021 15:08:20 +0000 (15:08 +0000)]
code-comments in MMU

2 years agoprefer not to invert when doing if/else.
Luke Kenneth Casson Leighton [Mon, 20 Dec 2021 15:01:38 +0000 (15:01 +0000)]
prefer not to invert when doing if/else.

2 years agomore code-comments
Luke Kenneth Casson Leighton [Mon, 20 Dec 2021 13:42:09 +0000 (13:42 +0000)]
more code-comments

2 years agoadd RTPDE - Radit Tree Page Directory Entry - Record and use it in MMU
Luke Kenneth Casson Leighton [Mon, 20 Dec 2021 13:38:44 +0000 (13:38 +0000)]
add RTPDE - Radit Tree Page Directory Entry - Record and use it in MMU
RTPDE is different from RTPTE

2 years agoadd (and ues) PRTBL Record in MMU
Luke Kenneth Casson Leighton [Mon, 20 Dec 2021 13:14:12 +0000 (13:14 +0000)]
add (and ues) PRTBL Record in MMU
PRTBL: Page Table Record.  it is identical in format and naming PGTBL

2 years agocreate PGTBL Record and use it in MMU page_table_idle
Luke Kenneth Casson Leighton [Mon, 20 Dec 2021 12:53:11 +0000 (12:53 +0000)]
create PGTBL Record and use it in MMU page_table_idle

2 years agoadd hard stop address in ifetch unit test, bit of a mess:
Luke Kenneth Casson Leighton [Sun, 19 Dec 2021 21:26:25 +0000 (21:26 +0000)]
add hard stop address in ifetch unit test, bit of a mess:
TestIssuerFSM is just being caught on the edge of attempting to execute
another instruction at a TRAP point

2 years agoset terminate if core terminate requested
Luke Kenneth Casson Leighton [Sun, 19 Dec 2021 15:54:15 +0000 (15:54 +0000)]
set terminate if core terminate requested
rather than override what is in TestIssuerBase, which examines PC for
a DBG DMI Halt condition (stop_addr_o)

2 years agocode-comments
Luke Kenneth Casson Leighton [Sun, 19 Dec 2021 15:49:07 +0000 (15:49 +0000)]
code-comments

2 years agoadd DMI STOPADDR register and use it in HDLRunner to halt simulations
Luke Kenneth Casson Leighton [Sun, 19 Dec 2021 15:47:13 +0000 (15:47 +0000)]
add DMI STOPADDR register and use it in HDLRunner to halt simulations
at exactly the right point.  very useful also for gdb hardware-level
breakpoints

2 years agobreak out when core is stopped in HDLRunner
Luke Kenneth Casson Leighton [Sun, 19 Dec 2021 15:03:55 +0000 (15:03 +0000)]
break out when core is stopped in HDLRunner
should be using DMI status check but this is quick

2 years agoadd link to XICS bugreport
Luke Kenneth Casson Leighton [Sat, 18 Dec 2021 23:49:06 +0000 (23:49 +0000)]
add link to XICS bugreport

2 years agosort out reset signalling after tracking down Simulation() bug
Luke Kenneth Casson Leighton [Sat, 18 Dec 2021 15:37:38 +0000 (15:37 +0000)]
sort out reset signalling after tracking down Simulation() bug

2 years agoadd icache/dcache/mmu unit test for TestIssuer
Luke Kenneth Casson Leighton [Sat, 18 Dec 2021 12:05:15 +0000 (12:05 +0000)]
add icache/dcache/mmu unit test for TestIssuer
this is a work-in-progress

2 years agoget instructions to re-run in issuer after I-Cache TLB lookup
Luke Kenneth Casson Leighton [Sat, 18 Dec 2021 02:19:06 +0000 (02:19 +0000)]
get instructions to re-run in issuer after I-Cache TLB lookup

2 years agoforgot to connect up I-Cache to MMU
Luke Kenneth Casson Leighton [Sat, 18 Dec 2021 01:57:20 +0000 (01:57 +0000)]
forgot to connect up I-Cache to MMU

2 years agomove connection of bus.stall in icache.py,
Luke Kenneth Casson Leighton [Sat, 18 Dec 2021 01:57:04 +0000 (01:57 +0000)]
move connection of bus.stall in icache.py,
only create a fake bus.stall if ibus does not have a stall signal

2 years agotidyup
Luke Kenneth Casson Leighton [Sat, 18 Dec 2021 01:22:06 +0000 (01:22 +0000)]
tidyup

2 years agotlb_req_index is TLB_BITS long not TLB_SIZE
Luke Kenneth Casson Leighton [Sat, 18 Dec 2021 01:19:40 +0000 (01:19 +0000)]
tlb_req_index is TLB_BITS long not TLB_SIZE

2 years agowhoops, a Simulation bug, dcache bus ack Signal needed to be
Luke Kenneth Casson Leighton [Thu, 16 Dec 2021 17:07:58 +0000 (17:07 +0000)]
whoops, a Simulation bug, dcache bus ack Signal needed to be
copied into a separate combinatorial Signal

2 years agogive names to MMU records
Luke Kenneth Casson Leighton [Thu, 16 Dec 2021 14:55:38 +0000 (14:55 +0000)]
give names to MMU records

2 years agoset_mmu_spr was using the slow-SPR index for the regfile
Luke Kenneth Casson Leighton [Thu, 16 Dec 2021 14:37:06 +0000 (14:37 +0000)]
set_mmu_spr was using the slow-SPR index for the regfile
not the actual 10-bit SPR number.  hence trying to set PRTBL
fails

2 years agowhoops remove duplicate code (cut/paste error) no harm done
Luke Kenneth Casson Leighton [Thu, 16 Dec 2021 14:07:09 +0000 (14:07 +0000)]
whoops remove duplicate code (cut/paste error) no harm done

2 years agoremove more unneeded code
Luke Kenneth Casson Leighton [Wed, 15 Dec 2021 20:15:56 +0000 (20:15 +0000)]
remove more unneeded code

2 years agoread MSR.PR and MSR.DR and update ICache priv/virt moed during fetch
Luke Kenneth Casson Leighton [Wed, 15 Dec 2021 15:49:45 +0000 (15:49 +0000)]
read MSR.PR and MSR.DR and update ICache priv/virt moed during fetch

2 years agoremove more of SVP64 from TestIssuerInternalInOrder
Luke Kenneth Casson Leighton [Wed, 15 Dec 2021 15:20:33 +0000 (15:20 +0000)]
remove more of SVP64 from TestIssuerInternalInOrder

2 years agoremove update of pc, msr and svstate from TestIssuerInOrder
Luke Kenneth Casson Leighton [Wed, 15 Dec 2021 15:16:30 +0000 (15:16 +0000)]
remove update of pc, msr and svstate from TestIssuerInOrder

2 years agomove update of pc, msr and svstate into TestIssuerBase
Luke Kenneth Casson Leighton [Wed, 15 Dec 2021 15:15:45 +0000 (15:15 +0000)]
move update of pc, msr and svstate into TestIssuerBase

2 years agocomment-out TestIssuerInternalInorder for now
Luke Kenneth Casson Leighton [Wed, 15 Dec 2021 14:58:10 +0000 (14:58 +0000)]
comment-out TestIssuerInternalInorder for now

2 years agomove alternative TestIssuerInternalInOrder to new file
Luke Kenneth Casson Leighton [Wed, 15 Dec 2021 14:56:36 +0000 (14:56 +0000)]
move alternative TestIssuerInternalInOrder to new file
soc/simple/inorder.py

2 years agosplit out common elaboratable code from TestIssuer,
Luke Kenneth Casson Leighton [Wed, 15 Dec 2021 13:28:48 +0000 (13:28 +0000)]
split out common elaboratable code from TestIssuer,
move it to TestIssuerBase.

2 years agobig split-out of common functions in TestIssuer to TestIssuerBase
Luke Kenneth Casson Leighton [Wed, 15 Dec 2021 13:14:33 +0000 (13:14 +0000)]
big split-out of common functions in TestIssuer to TestIssuerBase

2 years agosimplifying / tidyup of TestIssuer to get CoreState
Luke Kenneth Casson Leighton [Wed, 15 Dec 2021 13:05:12 +0000 (13:05 +0000)]
simplifying / tidyup of TestIssuer to get CoreState

2 years agosort out MSR, read/write in same way as PC/SVSTATE in TestIssuer
Luke Kenneth Casson Leighton [Wed, 15 Dec 2021 12:59:48 +0000 (12:59 +0000)]
sort out MSR, read/write in same way as PC/SVSTATE in TestIssuer

2 years agowhoops accidentally commented out setup of instructions
Luke Kenneth Casson Leighton [Wed, 15 Dec 2021 12:45:21 +0000 (12:45 +0000)]
whoops accidentally commented out setup of instructions
in setup_i_memory

2 years agoget fetch_failed working with no MMU
Luke Kenneth Casson Leighton [Wed, 15 Dec 2021 12:39:24 +0000 (12:39 +0000)]
get fetch_failed working with no MMU

2 years agotest_loadstore1.py: test_loadstore1_ifetch_multi now working
Tobias Platen [Tue, 14 Dec 2021 17:48:33 +0000 (18:48 +0100)]
test_loadstore1.py: test_loadstore1_ifetch_multi now working

2 years agotrying to get TestIssuer FSM to respond correctly to fetch exceptions
Luke Kenneth Casson Leighton [Tue, 14 Dec 2021 17:02:38 +0000 (17:02 +0000)]
trying to get TestIssuer FSM to respond correctly to fetch exceptions

2 years agoget OP_FETCH_FAILED to respond/return an exception correctly
Luke Kenneth Casson Leighton [Tue, 14 Dec 2021 17:02:10 +0000 (17:02 +0000)]
get OP_FETCH_FAILED to respond/return an exception correctly

2 years agoupdate wb_get memory with instructions if required
Luke Kenneth Casson Leighton [Tue, 14 Dec 2021 17:01:29 +0000 (17:01 +0000)]
update wb_get memory with instructions if required
this is for running TestIssuer with rom={some dictionary}"

2 years agofix test_loadstore1_ifetch_multi() in test_loadstore1.py
Tobias Platen [Tue, 14 Dec 2021 15:56:28 +0000 (16:56 +0100)]
fix test_loadstore1_ifetch_multi() in test_loadstore1.py

2 years agowip test case for virtual address fetch using fetch interface
Tobias Platen [Tue, 14 Dec 2021 14:30:35 +0000 (15:30 +0100)]
wip test case for virtual address fetch using fetch interface

2 years agofix test_loadstore1_ifetch_multi()
Tobias Platen [Tue, 14 Dec 2021 12:27:41 +0000 (13:27 +0100)]
fix test_loadstore1_ifetch_multi()

2 years agoGitLab-CI: Increase clone depth
Jonathan Neuschäfer [Mon, 13 Dec 2021 23:03:35 +0000 (00:03 +0100)]
GitLab-CI: Increase clone depth

Currently, GitLab-CI fails with this error:

  error: Server does not allow request for unadvertised object d96f737c0a53dde983060522816bbef016b449ce
  Fetched in submodule path 'pinmux', but it did not contain d96f737c0a53dde983060522816bbef016b449ce. Direct fetching of that commit failed.

Fix it by increasing the clone depth from the default of 50 to 500.

2 years agoMMU LOOKUP for fetch failed, priv mode is inversion of MSR.PR
Luke Kenneth Casson Leighton [Tue, 14 Dec 2021 00:46:53 +0000 (00:46 +0000)]
MMU LOOKUP for fetch failed, priv mode is inversion of MSR.PR

2 years agolink MSR.PR into MMU FSM OP_FETCH_FAILED
Luke Kenneth Casson Leighton [Tue, 14 Dec 2021 00:44:48 +0000 (00:44 +0000)]
link MSR.PR into MMU FSM OP_FETCH_FAILED

2 years agoreturn temporarily to older version of pinmux submodule
Luke Kenneth Casson Leighton [Mon, 13 Dec 2021 22:32:24 +0000 (22:32 +0000)]
return temporarily to older version of pinmux submodule

2 years agorequest a flush of icache to clear the instruction-fault state
Luke Kenneth Casson Leighton [Mon, 13 Dec 2021 18:16:31 +0000 (18:16 +0000)]
request a flush of icache to clear the instruction-fault state
when an exception is identified
g

2 years agotry to get multi test running
Tobias Platen [Mon, 13 Dec 2021 18:04:40 +0000 (19:04 +0100)]
try to get multi test running

2 years agocomments about test_loadstore1_ifetch()
Tobias Platen [Mon, 13 Dec 2021 15:07:12 +0000 (16:07 +0100)]
comments about test_loadstore1_ifetch()

2 years agofix test_loadstore1.py with MSR=PR/DR
Luke Kenneth Casson Leighton [Mon, 13 Dec 2021 14:22:17 +0000 (14:22 +0000)]
fix test_loadstore1.py with MSR=PR/DR
for invalid test pr=1 but for others pr=0

2 years agoset pr=0 because privileged mode is pr=0 not pr=1
Luke Kenneth Casson Leighton [Mon, 13 Dec 2021 14:19:59 +0000 (14:19 +0000)]
set pr=0 because privileged mode is pr=0 not pr=1

2 years agoadd in missing MSRSpec import
Luke Kenneth Casson Leighton [Mon, 13 Dec 2021 14:16:00 +0000 (14:16 +0000)]
add in missing MSRSpec import

2 years agocommented-out code
Luke Kenneth Casson Leighton [Mon, 13 Dec 2021 14:14:33 +0000 (14:14 +0000)]
commented-out code

2 years agoupdate MMU PortInterface Test (misalign)
Tobias Platen [Mon, 13 Dec 2021 13:40:39 +0000 (14:40 +0100)]
update MMU PortInterface Test (misalign)

2 years agocleanup test_ldst_pi.py
Tobias Platen [Mon, 13 Dec 2021 13:34:23 +0000 (14:34 +0100)]
cleanup test_ldst_pi.py

2 years agoupdate old TestMicrowattMemoryPortInterface
Tobias Platen [Mon, 13 Dec 2021 13:27:51 +0000 (14:27 +0100)]
update old TestMicrowattMemoryPortInterface

2 years agoreplace msr_pr with msr
Tobias Platen [Mon, 13 Dec 2021 13:26:37 +0000 (14:26 +0100)]
replace msr_pr with msr

2 years agocleanup test_dcbz_pi.py
Tobias Platen [Mon, 13 Dec 2021 13:17:45 +0000 (14:17 +0100)]
cleanup test_dcbz_pi.py

2 years agofix up pr/dr/sf in PortInterfaceBase
Luke Kenneth Casson Leighton [Mon, 13 Dec 2021 13:08:53 +0000 (13:08 +0000)]
fix up pr/dr/sf in PortInterfaceBase

2 years agopass in new MSRSpec to test_loadstore1.py not msr_pr=1
Luke Kenneth Casson Leighton [Mon, 13 Dec 2021 13:06:53 +0000 (13:06 +0000)]
pass in new MSRSpec to test_loadstore1.py not msr_pr=1

2 years agoconvert PortInterfaceBase to pass msr not msr_pr
Luke Kenneth Casson Leighton [Mon, 13 Dec 2021 13:01:58 +0000 (13:01 +0000)]
convert PortInterfaceBase to pass msr not msr_pr
https://bugs.libre-soc.org/show_bug.cgi?id=756

2 years agoconvert LoadStore1 to new msr.pr/dr/sf
Luke Kenneth Casson Leighton [Mon, 13 Dec 2021 13:00:54 +0000 (13:00 +0000)]
convert LoadStore1 to new msr.pr/dr/sf
https://bugs.libre-soc.org/show_bug.cgi?id=756

2 years agoadd msr to MMU Op Subset record
Luke Kenneth Casson Leighton [Mon, 13 Dec 2021 12:55:03 +0000 (12:55 +0000)]
add msr to MMU Op Subset record

2 years agouse NamedTuple pr in test_pi2ls
Tobias Platen [Mon, 13 Dec 2021 12:53:53 +0000 (13:53 +0100)]
use NamedTuple pr in test_pi2ls

2 years agostill have to import MSRSpec
Luke Kenneth Casson Leighton [Mon, 13 Dec 2021 12:43:15 +0000 (12:43 +0000)]
still have to import MSRSpec

2 years agoconnect up PortInterface priv_mode, virt_mode and mode_32bit
Luke Kenneth Casson Leighton [Mon, 13 Dec 2021 12:41:23 +0000 (12:41 +0000)]
connect up PortInterface priv_mode, virt_mode and mode_32bit
to MSR.PR, DR and SF.
https://bugs.libre-soc.org/show_bug.cgi?id=756

2 years agoMerge branch 'master' of ssh://git.libre-riscv.org:922/soc
Tobias Platen [Mon, 13 Dec 2021 12:36:34 +0000 (13:36 +0100)]
Merge branch 'master' of ssh://git.libre-riscv.org:922/soc

2 years agoconstruct an MSRSpec in PortInterfaceBase (not used yet)
Luke Kenneth Casson Leighton [Mon, 13 Dec 2021 12:35:02 +0000 (12:35 +0000)]
construct an MSRSpec in PortInterfaceBase (not used yet)

2 years agoremove redundant MSRSpec from pimem
Tobias Platen [Mon, 13 Dec 2021 12:34:52 +0000 (13:34 +0100)]
remove redundant MSRSpec from pimem

2 years agowhoops wrong variable names
Luke Kenneth Casson Leighton [Mon, 13 Dec 2021 12:32:31 +0000 (12:32 +0000)]
whoops wrong variable names

2 years agorename msr_pr to priv_mode in LDSTCompUnit
Luke Kenneth Casson Leighton [Mon, 13 Dec 2021 12:31:58 +0000 (12:31 +0000)]
rename msr_pr to priv_mode in LDSTCompUnit

2 years agoTODO comments about using MSRspec
Luke Kenneth Casson Leighton [Mon, 13 Dec 2021 12:29:06 +0000 (12:29 +0000)]
TODO comments about using MSRspec

2 years agochange PortInterface naming to msr not msr_pr in set_wr_addr
Luke Kenneth Casson Leighton [Mon, 13 Dec 2021 12:26:35 +0000 (12:26 +0000)]
change PortInterface naming to msr not msr_pr in set_wr_addr
and set_rd_addr.  the name-change does not affect any code at the moment

2 years agoadd namedtuple proposed by lkcl in chat
Tobias Platen [Mon, 13 Dec 2021 12:01:45 +0000 (13:01 +0100)]
add namedtuple proposed by lkcl in chat

2 years agoadd signals to port interface as descibed in bug 756
Tobias Platen [Mon, 13 Dec 2021 10:41:24 +0000 (11:41 +0100)]
add signals to port interface as descibed in bug 756

2 years agomore work on test_loadstore1_ifetch_multi()
Tobias Platen [Mon, 13 Dec 2021 09:45:50 +0000 (10:45 +0100)]
more work on test_loadstore1_ifetch_multi()

2 years agoset and reset instruction fault so it does not occur twice
Luke Kenneth Casson Leighton [Sun, 12 Dec 2021 21:08:35 +0000 (21:08 +0000)]
set and reset instruction fault so it does not occur twice

2 years agowhen an exception happens, if it is a fetch_failed take the
Luke Kenneth Casson Leighton [Sun, 12 Dec 2021 20:45:49 +0000 (20:45 +0000)]
when an exception happens, if it is a fetch_failed take the
exception from the MMU not from LDST.

at some point need a much more sophisticated way of detecting which
unit created which exception

2 years agodelay MMU LOOKUP done by one clock so that the exception matches timing
Luke Kenneth Casson Leighton [Sun, 12 Dec 2021 20:45:04 +0000 (20:45 +0000)]
delay MMU LOOKUP done by one clock so that the exception matches timing

2 years agobring MMU exception out where AllFunctionUnits (and then core)
Luke Kenneth Casson Leighton [Sun, 12 Dec 2021 20:44:26 +0000 (20:44 +0000)]
bring MMU exception out where AllFunctionUnits (and then core)
can get at it

2 years agobring exception out from MMU FSM, correct "done"
Luke Kenneth Casson Leighton [Sun, 12 Dec 2021 20:18:46 +0000 (20:18 +0000)]
bring exception out from MMU FSM, correct "done"
signal output on OP_FETCH_FAILED

2 years agoadd LDSTException output to MMU
Luke Kenneth Casson Leighton [Sun, 12 Dec 2021 20:05:50 +0000 (20:05 +0000)]
add LDSTException output to MMU

2 years agodrat, a test inverting the instruction made it into the git history
Luke Kenneth Casson Leighton [Sun, 12 Dec 2021 19:10:36 +0000 (19:10 +0000)]
drat, a test inverting the instruction made it into the git history

2 years agostarting to hack in fetch failed (including OP_FETCH_FAILED)
Luke Kenneth Casson Leighton [Sun, 12 Dec 2021 18:56:13 +0000 (18:56 +0000)]
starting to hack in fetch failed (including OP_FETCH_FAILED)
going really badly as far as code-readability and clean design is concerned
but is progressing

a truly dreadful hack: OP_TRAP works (LDST Exceptions) because the
main decoder (PowerDecoder2) is used by core for the Trap pipeline.

unnnnfortunately... for MMU, a *Satellite* decoder (PowerDecodeSubset)
is used.  and Satellite decoders *only* understand *instructions*.
(which they part-decode locally).

therefore a manual override of the satellite decoder insn_type
and fn_unit is required when OP_FETCH_FAILED occurs.

truly awful.

2 years agoprint debugs established that when a wb_get memory dictionary is
Luke Kenneth Casson Leighton [Sun, 12 Dec 2021 15:47:10 +0000 (15:47 +0000)]
print debugs established that when a wb_get memory dictionary is
passed in, trying to use setup_i_memory and setup_tst_memory will not
work.

using wb_get has to be established a different way

2 years agoset fetch_failed into PowerDecoder2 combinatorially
Luke Kenneth Casson Leighton [Sun, 12 Dec 2021 15:44:50 +0000 (15:44 +0000)]
set fetch_failed into PowerDecoder2 combinatorially

2 years agoin a terrible botched way, get at I-Cache and set it up
Luke Kenneth Casson Leighton [Sun, 12 Dec 2021 13:15:51 +0000 (13:15 +0000)]
in a terrible botched way, get at I-Cache and set it up
this is for adding in I-Cache and MMU into core.

2 years agofix bug in unit test, forgot that wb_get mem dict is 64-bit wide data
Luke Kenneth Casson Leighton [Sat, 11 Dec 2021 23:49:48 +0000 (23:49 +0000)]
fix bug in unit test, forgot that wb_get mem dict is 64-bit wide data
it cannot cope with addresses non-aligned to 64-bit boundary