soc.git
4 years agomissed cd build
Luke Kenneth Casson Leighton [Thu, 26 Mar 2020 11:16:05 +0000 (11:16 +0000)]
missed cd build

4 years agoadd README describing build process for simulator (gdb ppc)
Luke Kenneth Casson Leighton [Thu, 26 Mar 2020 11:08:29 +0000 (11:08 +0000)]
add README describing build process for simulator (gdb ppc)

4 years agoadd pygdbmi to dependencies
Luke Kenneth Casson Leighton [Thu, 26 Mar 2020 11:03:28 +0000 (11:03 +0000)]
add pygdbmi to dependencies

4 years agowait for communication with closing program and close the stdin/out pipes
Luke Kenneth Casson Leighton [Thu, 26 Mar 2020 11:01:33 +0000 (11:01 +0000)]
wait for communication with closing program and close the stdin/out pipes

4 years agoDirectly compare simulator with qemu
Michael Nolan [Wed, 25 Mar 2020 22:38:18 +0000 (18:38 -0400)]
Directly compare simulator with qemu

I'm getting an error where it says some files are still open, but I
can't figure out what they are

4 years agoAssemble whole program instead of instruction by instruction
Michael Nolan [Wed, 25 Mar 2020 21:16:07 +0000 (17:16 -0400)]
Assemble whole program instead of instruction by instruction

4 years agoAdd rudimentary python qemu interface
Michael Nolan [Wed, 25 Mar 2020 20:44:17 +0000 (16:44 -0400)]
Add rudimentary python qemu interface

4 years agoAdd instructions for how to launch qemu
Michael Nolan [Wed, 25 Mar 2020 17:26:15 +0000 (13:26 -0400)]
Add instructions for how to launch qemu

4 years agoAdd qemu test directory
Michael Nolan [Wed, 25 Mar 2020 17:23:16 +0000 (13:23 -0400)]
Add qemu test directory

4 years agochange name of test function in addr_split
Luke Kenneth Casson Leighton [Tue, 24 Mar 2020 11:14:13 +0000 (11:14 +0000)]
change name of test function in addr_split

4 years agowhitespace
Luke Kenneth Casson Leighton [Tue, 24 Mar 2020 10:59:18 +0000 (10:59 +0000)]
whitespace

4 years agowhitespace cleanup
Luke Kenneth Casson Leighton [Tue, 24 Mar 2020 10:57:56 +0000 (10:57 +0000)]
whitespace cleanup

4 years agoadd cross-references to bugreports and wiki
Luke Kenneth Casson Leighton [Tue, 24 Mar 2020 10:26:10 +0000 (10:26 +0000)]
add cross-references to bugreports and wiki

4 years agoadd routing of store data through splitters
Luke Kenneth Casson Leighton [Tue, 24 Mar 2020 10:24:02 +0000 (10:24 +0000)]
add routing of store data through splitters

4 years agomove ashift out to common area
Luke Kenneth Casson Leighton [Tue, 24 Mar 2020 10:13:24 +0000 (10:13 +0000)]
move ashift out to common area

4 years agoImplement load and store of bytes, halfwords, and words
Michael Nolan [Mon, 23 Mar 2020 20:01:10 +0000 (16:01 -0400)]
Implement load and store of bytes, halfwords, and words

4 years agoProperly sign extend immediates
Michael Nolan [Mon, 23 Mar 2020 18:40:22 +0000 (14:40 -0400)]
Properly sign extend immediates

4 years agoFix broken test
Michael Nolan [Mon, 23 Mar 2020 18:24:20 +0000 (14:24 -0400)]
Fix broken test

4 years agoAdd support for extended/indexed ld/st
Michael Nolan [Mon, 23 Mar 2020 15:46:36 +0000 (11:46 -0400)]
Add support for extended/indexed ld/st

4 years agohmm start adding st in (half done)
Luke Kenneth Casson Leighton [Mon, 23 Mar 2020 18:05:23 +0000 (18:05 +0000)]
hmm start adding st in (half done)

4 years agoAdd memory loads and stores to simulator
Michael Nolan [Mon, 23 Mar 2020 14:53:53 +0000 (10:53 -0400)]
Add memory loads and stores to simulator

4 years agoBegin adding backend simulator
Michael Nolan [Mon, 23 Mar 2020 14:21:44 +0000 (10:21 -0400)]
Begin adding backend simulator

4 years agoMove gnu assembler interface to separate file
Michael Nolan [Mon, 23 Mar 2020 13:41:35 +0000 (09:41 -0400)]
Move gnu assembler interface to separate file

4 years agosplit sim classes out into separate module
Luke Kenneth Casson Leighton [Mon, 23 Mar 2020 13:46:19 +0000 (13:46 +0000)]
split sim classes out into separate module

4 years agoadd twin partial address mapper class
Luke Kenneth Casson Leighton [Mon, 23 Mar 2020 10:05:22 +0000 (10:05 +0000)]
add twin partial address mapper class
designed to be used with LDSTSplitter which creates two addresses for
misaligned LD/STs across cache-lines

4 years agosort out unit test for address split
Luke Kenneth Casson Leighton [Mon, 23 Mar 2020 09:24:06 +0000 (09:24 +0000)]
sort out unit test for address split

4 years agoget AddrSplitter working for data len=8
Luke Kenneth Casson Leighton [Sun, 22 Mar 2020 14:38:37 +0000 (14:38 +0000)]
get AddrSplitter working for data len=8

4 years agoworking on simulation to test Address Splitter
Luke Kenneth Casson Leighton [Sun, 22 Mar 2020 13:56:46 +0000 (13:56 +0000)]
working on simulation to test Address Splitter

4 years agolink up output from ld1/ld2 and merge into request
Luke Kenneth Casson Leighton [Sun, 22 Mar 2020 12:34:01 +0000 (12:34 +0000)]
link up output from ld1/ld2 and merge into request

4 years agostart putting LDSTSplitter together
Luke Kenneth Casson Leighton [Sun, 22 Mar 2020 11:33:44 +0000 (11:33 +0000)]
start putting LDSTSplitter together

4 years agoset bigendian=1 in formal proofs of decoder (TODO: bigendian=0)
Luke Kenneth Casson Leighton [Sat, 21 Mar 2020 19:02:18 +0000 (19:02 +0000)]
set bigendian=1 in formal proofs of decoder (TODO: bigendian=0)

4 years agowhoops cut/paste error
Luke Kenneth Casson Leighton [Sat, 21 Mar 2020 18:58:39 +0000 (18:58 +0000)]
whoops cut/paste error

4 years agostart on address splitter, idea is to use Queues
Luke Kenneth Casson Leighton [Sat, 21 Mar 2020 18:55:33 +0000 (18:55 +0000)]
start on address splitter, idea is to use Queues

4 years agomention instruction fetch mapping section
Luke Kenneth Casson Leighton [Sat, 21 Mar 2020 12:12:00 +0000 (12:12 +0000)]
mention instruction fetch mapping section

4 years agoshorten variables, add comments
Luke Kenneth Casson Leighton [Sat, 21 Mar 2020 11:48:14 +0000 (11:48 +0000)]
shorten variables, add comments

4 years agoadd option to switch endianness on gnu as
Luke Kenneth Casson Leighton [Sat, 21 Mar 2020 11:46:11 +0000 (11:46 +0000)]
add option to switch endianness on gnu as

4 years agoadd big/little byte-reversing
Luke Kenneth Casson Leighton [Sat, 21 Mar 2020 11:08:29 +0000 (11:08 +0000)]
add big/little byte-reversing

4 years agoFix proof_decoder2
Michael Nolan [Fri, 20 Mar 2020 14:50:47 +0000 (10:50 -0400)]
Fix proof_decoder2

4 years agoDelete log messages in power_fields and power_fieldsn
Michael Nolan [Fri, 20 Mar 2020 14:41:18 +0000 (10:41 -0400)]
Delete log messages in power_fields and power_fieldsn

4 years agoMinor cleanup
Michael Nolan [Fri, 20 Mar 2020 14:40:54 +0000 (10:40 -0400)]
Minor cleanup

4 years agoAdd test for branch to lr/ctr
Michael Nolan [Fri, 20 Mar 2020 14:38:28 +0000 (10:38 -0400)]
Add test for branch to lr/ctr

4 years agoAdd tests for branch instructions
Michael Nolan [Fri, 20 Mar 2020 14:17:11 +0000 (10:17 -0400)]
Add tests for branch instructions

4 years agoAdd test for rotate/shift instructions
Michael Nolan [Fri, 20 Mar 2020 14:07:53 +0000 (10:07 -0400)]
Add test for rotate/shift instructions

4 years agoRemove unneeded condition register decoder
Michael Nolan [Fri, 20 Mar 2020 13:57:27 +0000 (09:57 -0400)]
Remove unneeded condition register decoder

4 years agoAdd test for cmp with register
Michael Nolan [Thu, 19 Mar 2020 19:21:43 +0000 (15:21 -0400)]
Add test for cmp with register

4 years agoAdd tests for load/store with immediate offset
Michael Nolan [Thu, 19 Mar 2020 18:48:31 +0000 (14:48 -0400)]
Add tests for load/store with immediate offset

4 years agoAdd ld and st instructions to the reg/reg test
Michael Nolan [Thu, 19 Mar 2020 18:35:01 +0000 (14:35 -0400)]
Add ld and st instructions to the reg/reg test

4 years agoAdd checks for the decoding of RC (the . in some instructions)
Michael Nolan [Thu, 19 Mar 2020 18:24:39 +0000 (14:24 -0400)]
Add checks for the decoding of RC (the . in some instructions)

4 years agoAdd tests for register+immediate ops
Michael Nolan [Thu, 19 Mar 2020 18:08:29 +0000 (14:08 -0400)]
Add tests for register+immediate ops

Fix issue with decoder where a signed shifted immediate wasn't shifted
by the right amount

4 years agoFactor out instruction generation and testing from simulation
Michael Nolan [Thu, 19 Mar 2020 17:38:44 +0000 (13:38 -0400)]
Factor out instruction generation and testing from simulation

4 years agoCleanup test_decoder_gas.py
Michael Nolan [Thu, 19 Mar 2020 15:43:25 +0000 (11:43 -0400)]
Cleanup test_decoder_gas.py

4 years agoAdd assertions for input registers
Michael Nolan [Thu, 19 Mar 2020 15:41:03 +0000 (11:41 -0400)]
Add assertions for input registers

4 years agofix silly errors in power_fieldsn.py
Luke Kenneth Casson Leighton [Thu, 19 Mar 2020 06:53:36 +0000 (06:53 +0000)]
fix silly errors in power_fieldsn.py

4 years agoinvert bits of field in decoder (not instruction bits)
Luke Kenneth Casson Leighton [Thu, 19 Mar 2020 02:58:38 +0000 (02:58 +0000)]
invert bits of field in decoder (not instruction bits)

4 years agoBegin adding a test using GNU AS
Michael Nolan [Wed, 18 Mar 2020 15:48:04 +0000 (11:48 -0400)]
Begin adding a test using GNU AS

4 years agoAdd proof that all other opcodes decode to INVALID
Michael Nolan [Wed, 18 Mar 2020 13:35:07 +0000 (09:35 -0400)]
Add proof that all other opcodes decode to INVALID

4 years agoFix bug where enum values weren't getting set to int
Michael Nolan [Wed, 18 Mar 2020 13:34:45 +0000 (09:34 -0400)]
Fix bug where enum values weren't getting set to int

4 years agouse function which reverses bit-order
Luke Kenneth Casson Leighton [Wed, 18 Mar 2020 16:10:32 +0000 (16:10 +0000)]
use function which reverses bit-order

4 years agocomment reverse-order of bit-fields
Luke Kenneth Casson Leighton [Wed, 18 Mar 2020 16:06:30 +0000 (16:06 +0000)]
comment reverse-order of bit-fields

4 years agodone, http://bugs.libre-riscv.org/show_bug.cgi?id=261
Luke Kenneth Casson Leighton [Wed, 18 Mar 2020 13:59:48 +0000 (13:59 +0000)]
done, bugs.libre-riscv.org/show_bug.cgi?id=261

4 years agoCreate SPR enum from sprs.csv
Michael Nolan [Wed, 18 Mar 2020 13:30:03 +0000 (09:30 -0400)]
Create SPR enum from sprs.csv

4 years agoAdd more to decoder proof
Michael Nolan [Wed, 18 Mar 2020 13:00:05 +0000 (09:00 -0400)]
Add more to decoder proof

4 years agoBegin adding proof for decoder stage 1
Michael Nolan [Mon, 16 Mar 2020 19:15:49 +0000 (15:15 -0400)]
Begin adding proof for decoder stage 1

4 years agoadd comment about SPRs CSV
Luke Kenneth Casson Leighton [Wed, 18 Mar 2020 12:12:21 +0000 (12:12 +0000)]
add comment about SPRs CSV

4 years agoadd comments
Luke Kenneth Casson Leighton [Wed, 18 Mar 2020 12:03:42 +0000 (12:03 +0000)]
add comments

4 years agoimport absolute paths
Luke Kenneth Casson Leighton [Wed, 18 Mar 2020 11:30:58 +0000 (11:30 +0000)]
import absolute paths

4 years agoclarify is_match manually
Luke Kenneth Casson Leighton [Mon, 16 Mar 2020 17:19:43 +0000 (17:19 +0000)]
clarify is_match manually

4 years agoadd exploratory unit test for partial address matching
Luke Kenneth Casson Leighton [Mon, 16 Mar 2020 13:18:48 +0000 (13:18 +0000)]
add exploratory unit test for partial address matching

4 years agocomment out addr_we_i, seems not to be used
Luke Kenneth Casson Leighton [Mon, 16 Mar 2020 12:39:28 +0000 (12:39 +0000)]
comment out addr_we_i, seems not to be used

4 years agoconnect up expander output, set up is_match to check bitmap and wrapped bitmap
Luke Kenneth Casson Leighton [Mon, 16 Mar 2020 12:39:03 +0000 (12:39 +0000)]
connect up expander output, set up is_match to check bitmap and wrapped bitmap
(crossing cache line boundary)

4 years agoconnect LenExpanders into PartialAddrBitmap
Luke Kenneth Casson Leighton [Mon, 16 Mar 2020 12:12:43 +0000 (12:12 +0000)]
connect LenExpanders into PartialAddrBitmap

4 years agocrossreference to bugreport
Luke Kenneth Casson Leighton [Sun, 15 Mar 2020 22:16:20 +0000 (22:16 +0000)]
crossreference to bugreport

4 years agoadd description of how PartialAddrBitmap works
Luke Kenneth Casson Leighton [Sun, 15 Mar 2020 22:15:42 +0000 (22:15 +0000)]
add description of how PartialAddrBitmap works

4 years ago add beginnings of link to lenexpanders
Luke Kenneth Casson Leighton [Sun, 15 Mar 2020 11:20:02 +0000 (11:20 +0000)]
 add beginnings of link to lenexpanders

4 years agoadd a LenExpand class which takes a (length, addr) pair,
Luke Kenneth Casson Leighton [Sat, 14 Mar 2020 17:50:58 +0000 (17:50 +0000)]
add a LenExpand class which takes a (length, addr) pair,
turns it into a bitmap of bytes that would be affected by that LD/ST

4 years agoadd beginnings of PartialAddrBitmap elaborate
Luke Kenneth Casson Leighton [Sat, 14 Mar 2020 11:56:07 +0000 (11:56 +0000)]
add beginnings of PartialAddrBitmap elaborate

4 years agoallow over-ride of address match function in PartialAddrMatch
Luke Kenneth Casson Leighton [Fri, 13 Mar 2020 22:36:19 +0000 (22:36 +0000)]
allow over-ride of address match function in PartialAddrMatch

4 years agofix more imports
Luke Kenneth Casson Leighton [Wed, 11 Mar 2020 18:19:08 +0000 (18:19 +0000)]
fix more imports

4 years agofix more imports
Luke Kenneth Casson Leighton [Wed, 11 Mar 2020 18:18:14 +0000 (18:18 +0000)]
fix more imports

4 years agoenable rvfi, fix imports
Luke Kenneth Casson Leighton [Wed, 11 Mar 2020 18:16:35 +0000 (18:16 +0000)]
enable rvfi, fix imports

4 years agodestarify debug
Luke Kenneth Casson Leighton [Wed, 11 Mar 2020 18:15:17 +0000 (18:15 +0000)]
destarify debug

4 years agodewildcardify units
Luke Kenneth Casson Leighton [Wed, 11 Mar 2020 17:17:46 +0000 (17:17 +0000)]
dewildcardify units

4 years agodewildcardify unitsg
Luke Kenneth Casson Leighton [Wed, 11 Mar 2020 17:10:35 +0000 (17:10 +0000)]
dewildcardify unitsg

4 years agosort out imports to get minerva generate working
Luke Kenneth Casson Leighton [Wed, 11 Mar 2020 17:05:20 +0000 (17:05 +0000)]
sort out imports to get minerva generate working

4 years agodewildcard core.py
Luke Kenneth Casson Leighton [Wed, 11 Mar 2020 17:02:24 +0000 (17:02 +0000)]
dewildcard core.py

4 years agodewildcard cache.py
Luke Kenneth Casson Leighton [Wed, 11 Mar 2020 16:54:29 +0000 (16:54 +0000)]
dewildcard cache.py

4 years agodewildcard stage.py
Luke Kenneth Casson Leighton [Wed, 11 Mar 2020 16:51:57 +0000 (16:51 +0000)]
dewildcard stage.py

4 years agodewildcard wishbone.py
Luke Kenneth Casson Leighton [Wed, 11 Mar 2020 16:49:49 +0000 (16:49 +0000)]
dewildcard wishbone.py

4 years agoreplace isa import
Luke Kenneth Casson Leighton [Wed, 11 Mar 2020 16:44:27 +0000 (16:44 +0000)]
replace isa import

4 years agode-starify csr.py
Luke Kenneth Casson Leighton [Wed, 11 Mar 2020 16:28:25 +0000 (16:28 +0000)]
de-starify csr.py

4 years agoimport minerva from soc.minerva
Luke Kenneth Casson Leighton [Wed, 11 Mar 2020 16:13:16 +0000 (16:13 +0000)]
import minerva from soc.minerva

4 years agoadd minerva source from https://github.com/lambdaconcept/minerva
Luke Kenneth Casson Leighton [Wed, 11 Mar 2020 16:10:51 +0000 (16:10 +0000)]
add minerva source from https://github.com/lambdaconcept/minerva

4 years agoAdd assertions that instruction fields are correct
Michael Nolan [Wed, 11 Mar 2020 14:17:26 +0000 (10:17 -0400)]
Add assertions that instruction fields are correct

4 years agoAdd test for remaining bits
Michael Nolan [Wed, 11 Mar 2020 13:21:35 +0000 (09:21 -0400)]
Add test for remaining bits

4 years agoAdd tests for DecodeOut and DecodeRC
Michael Nolan [Wed, 11 Mar 2020 13:12:52 +0000 (09:12 -0400)]
Add tests for DecodeOut and DecodeRC

4 years agostore ra in intermediate, to avoid creation of decoding twice
Luke Kenneth Casson Leighton [Wed, 11 Mar 2020 08:37:24 +0000 (08:37 +0000)]
store ra in intermediate, to avoid creation of decoding twice

4 years agoadd "done" signal to CompALU and LDSTCompALU to be able to select between the
Luke Kenneth Casson Leighton [Tue, 10 Mar 2020 20:38:05 +0000 (20:38 +0000)]
add "done" signal to CompALU and LDSTCompALU to be able to select between the
two types consistently

4 years agoinitial test LD comp unit in scoreboard
Luke Kenneth Casson Leighton [Tue, 10 Mar 2020 19:49:55 +0000 (19:49 +0000)]
initial test LD comp unit in scoreboard

4 years agohmmm set store latch based on go_rd_i
Luke Kenneth Casson Leighton [Tue, 10 Mar 2020 18:10:15 +0000 (18:10 +0000)]
hmmm set store latch based on go_rd_i

4 years agoadd ADD/ADDI test to LDSTCompUnit
Luke Kenneth Casson Leighton [Tue, 10 Mar 2020 18:00:54 +0000 (18:00 +0000)]
add ADD/ADDI test to LDSTCompUnit