soc.git
2020-09-07 Luke Kenneth... oe_ok renamed to oe, needed in regspec_decode_read
2020-09-07 Luke Kenneth... add insn and fn_unit to CompLDSTOpSubset
2020-09-07 Luke Kenneth... add pspec and opsubsetkls to CompUnits
2020-09-07 Cole Poiriericache.py commit translation progress, about one third...
2020-09-07 Luke Kenneth... make immediate decoding optional on-demand
2020-09-07 Luke Kenneth... whoops spelling mistake outOut_carry not outPut_carry
2020-09-07 Luke Kenneth... convert mul test to use Power Decode subset
2020-09-07 Luke Kenneth... convert shift_rot to subset decoder
2020-09-07 Luke Kenneth... convert branch test to PowerDecodeSubset form
2020-09-07 Luke Kenneth... convert CR to PowerDecodeSubset format
2020-09-07 Luke Kenneth... bit of a big reorg of data structures
2020-09-07 Luke Kenneth... split out PowerDecode2 into PowerDecodeSubset
2020-09-07 Luke Kenneth... large stack of moving stuff around in dcache
2020-09-07 Luke Kenneth... adjust indentation of dcache_slow
2020-09-07 Luke Kenneth... more dcache translation
2020-09-07 Luke Kenneth... add start on cache_ram.vhdl to nmigen conversion
2020-09-07 Luke Kenneth... more dcache translation
2020-09-07 Luke Kenneth... allow Decode2ToExecute1Type to take an opkls argument
2020-09-07 Luke Kenneth... whoops truncated the mb and me fields
2020-09-07 Luke Kenneth... minor reorg on PowerDecoder
2020-09-06 Luke Kenneth... comment, nothing unusual when Trap Type is DEC
2020-09-06 Luke Kenneth... decoder immediate b split out to DecodeBImm
2020-09-06 Luke Kenneth... decoder immediate a split out to DecodeAImm
2020-09-06 Luke Kenneth... add row subset selector for PowerDecode.
2020-09-06 Luke Kenneth... add row_subset (doesnt do anything yet)
2020-09-06 Luke Kenneth... pass col_subset throughout PowerDecoder
2020-09-06 Luke Kenneth... reorganise PowerOp to be dynamic
2020-09-06 Luke Kenneth... reorg of PowerOp to be able to dynamically subset it
2020-09-06 Luke Kenneth... grr, autopep8 messing up
2020-09-06 Luke Kenneth... copy dec SPR into decoder cur_state
2020-09-06 Luke Kenneth... add reset option to Register
2020-09-06 Luke Kenneth... wark-wark, fast regs is binary-addressed
2020-09-06 Luke Kenneth... add unit test for slow SPRs (SPRG0/1)
2020-09-06 Luke Kenneth... minor code-munge on SPR-to-FAST mapping
2020-09-06 Luke Kenneth... use with subTest in spr unit test
2020-09-06 Luke Kenneth... redo generation of microwatt.v from litex
2020-09-06 Luke Kenneth... add comments for DEC / TB
2020-09-06 Luke Kenneth... add a DEC/TB FSM to TestIssuer
2020-09-06 Luke Kenneth... move DEC and TB from StateRegs to FastRegs for several...
2020-09-06 Luke Kenneth... add DEC SPR to CoreState and PowerDecoder, activate...
2020-09-06 Luke Kenneth... add DEC and TB to State regfile
2020-09-06 Luke Kenneth... add DEC/TB SPRs to spr pipeline
2020-09-05 Luke Kenneth... add comments on MSR read
2020-09-05 Luke Kenneth... move GPIO IRQ to 15 to match microwatt modifications
2020-09-05 Luke Kenneth... hmmm XICS data being asserted on wb bus for too long
2020-09-05 Luke Kenneth... argh missed a VHDL "&" translating to Cat
2020-09-05 Luke Kenneth... reduce XICS address lookup by 2 bits
2020-09-05 Luke Kenneth... MSR read in INSN_READ only occurs for 1 cycle
2020-09-05 Luke Kenneth... sync on ICP eint
2020-09-05 Luke Kenneth... connect XICS core irq to Decode2 eint
2020-09-05 Luke Kenneth... whoops, combinatorial loop on pending_priority
2020-09-05 Luke Kenneth... use stbcix in test
2020-09-05 Luke Kenneth... XICS addresses in words: divide by 4
2020-09-05 Luke Kenneth... whoops, ICS in litex sim needs to be 0x1000 size region
2020-09-05 Luke Kenneth... add lwzcix unit test
2020-09-05 Luke Kenneth... increase wishbone address width to 29 for xics and...
2020-09-05 Luke Kenneth... submodule update
2020-09-05 Luke Kenneth... add simple GPIO wishbone bus to litex sim.py
2020-09-05 Luke Kenneth... add stbcix and lwzcix to power_enum list
2020-09-05 Luke Kenneth... add simple GPIO peripheral to verilog TestIssuer
2020-09-05 Luke Kenneth... move wb read/write to separate util test library and...
2020-09-05 Luke Kenneth... add simple wishbone GPIO peripheral
2020-09-05 Samuel A. Falvo IIAdd unit test replicating failing proof case
2020-09-04 Luke Kenneth... add sld test with RB=64 to see what happens
2020-09-04 Luke Kenneth... reduce CSR data width to 8 as an experiment
2020-09-04 Luke Kenneth... add UART reserved IRQ @ 0
2020-09-04 Luke Kenneth... add XICS memory regions, shrink litex CSR memmap size...
2020-09-04 Luke Kenneth... adding XICS wb slave devices to litex sim
2020-09-04 Luke Kenneth... bring out XICS ICS interrupt levels so that they can...
2020-09-04 Luke Kenneth... adding option to include XICS external interrupts.
2020-09-04 Luke Kenneth... add means to run hello_world.bin under simulation
2020-09-04 Jacob Lifshayupdate to match refactored power-instruction-analyzer API
2020-09-03 Samuel A. Falvo IIProvide full name and email in copyright notice.
2020-09-03 Luke Kenneth... do more on dcache conversion
2020-09-03 Luke Kenneth... testing microwatt 3.bin (2.bin ok)
2020-09-02 Luke Kenneth... when mtocrf FXM is 0, the CR has to be set to CR7
2020-09-02 Luke Kenneth... fix bug in cmpli (and cmplw)
2020-09-02 Luke Kenneth... sign-extend lhax needs 16-64, separate from lwax which...
2020-09-02 Luke Kenneth... add bc ctr regression test when CTR=0 and CTR=1
2020-09-02 Luke Kenneth... update submodule
2020-09-02 Luke Kenneth... bug in carry32 handling in OP_CMP
2020-09-02 Luke Kenneth... add cmpl regression test (one binary, one assembly)
2020-09-02 Luke Kenneth... add cmpl microwatt 1.bin test, cmpl
2020-09-02 Luke Kenneth... series of extensive modifications to fix long-standing...
2020-08-31 Luke Kenneth... add XER to fastregs and "construct" it in mfspr/mtspr
2020-08-30 Luke Kenneth... redo OP_CMP based on microwatt. L=1 had been ignored
2020-08-30 Luke Kenneth... reversal of FXM mask for one-hot selection in OP_MTCR...
2020-08-30 Luke Kenneth... working on dcache.py
2020-08-30 Luke Kenneth... tidyup on mul proof
2020-08-30 Luke Kenneth... set mul post_stage o.ok only when needed, and fix xer_s...
2020-08-30 Cole PoirierMerge branch 'master' of git.libre-soc.org:soc
2020-08-30 Cole Poiriericache.py commit progress, about a third through the...
2020-08-29 Samuel A. Falvo IIQualify XER_OV output in proof
2020-08-29 Samuel A. Falvo IIFix test breakage in MUL proofs
2020-08-29 Cole PoirierMerge branch 'master' of git.libre-soc.org:soc
2020-08-29 Cole Poiriermmu.py, dcache.py, mem_types.py change types capitaliza...
2020-08-29 Cole Poiriermem_types add more types from common.vhdl specifially...
2020-08-29 Cole Poiriermem_types.py arrange in alphabetical order for ease...
2020-08-29 Samuel A. Falvo IIBROKEN: xer_ov_o != dut.o.xer_ov.data ???!!!
2020-08-29 Cole Poiriermmu.py remove duplicate comment left over from mmu...
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