updates/018_2019may27_nlnet_grant_approved.mdwn

   1 The application for funding from NLnet, from back in November of last year,
   2 has been approved.  It means that we have EUR $50,000 to pay for full-time
   3 engineering work to be carried out over the next year, and to pay for
   4 bounty-style tasks.  For the right people, with the right skills, there
   5 is money now available.
   6
   7 However, this is not all: by splitting the tasks up into separate groups,
   8 and using a second European-based individual as the applicant, we can
   9 apply for a second grant (also of up to EUR $50,000).  In the next couple
  10 of days, we will put in an application for "Formal Mathematical Proofs"
  11 of the processor design.
  12
  13 There are several reasons for doing so.  The primary one is down to the
  14 fact that we anticipate this (commercial, libre) product to be closely
  15 and independently examined by third parties, to verify for themselves
  16 that it does not contain spying backdoor co-processors, as well as the
  17 usual security and correctness guarantees.  If there exist *formal
  18 mathematical proofs* that the processor and its sub-components operate
  19 correctly, that independent third-party verification task is a lot easier.
  20
  21 In addition, it turns out that when writing unit tests, using formal
  22 mathematical proofs makes for *complete* code coverage - far better
  23 than any other "comprehensive" multiple unit test technique could ever
  24 hope to achieve - with less code and not just better accuracy but *100%
  25 provable* accuracy.  Additional, much simpler unit tests can then be written
  26 which are more along the lines of "HOWTOs" - examples on how to use the
  27 unit.
  28
  29 This is one of those "epiphany" moments that, as a software engineer of
  30 25 years experience, has me stunned and wondering why on earth this is
  31 not more generally and widely deployed in software. The answer I believe
  32 is down to the nature of what a processor actually is.
  33
  34 A processor is developed much more along the lines of how functional programming
  35 works.  Functional programming can have formal mathematical proofs applied
  36 to it because for any given inputs, the output is *guaranteed* to be the same.
  37 This of course breaks down when the function has "side-effects," such as
  38 reading from a file or accessing other external state outside of the "control"
  39 of the function.  And, in the design of a processor, by the very nature
  40 of hardware, you simply cannot create a verilog module that has access to
  41 "files" or to "global variables."
  42
  43 In addition, hardware is based purely on boolean logic, and on if/else
  44 constructs.  In essence, then the *entire hardware design* has to be made
  45 according to far simpler rules than "normal" software is expected to conform
  46 to.  Even memory accesses in hardware have to be implemented according to
  47 these strict rules (we're *implementing* LOAD and STORE instructions here,
  48 not *using* those LOAD and STORE instructions).
  49
  50 Consequently, adding in formal proofs is a little bit easier, brings
  51 huge benefits as well in terms of code readability, reliability, and
  52 time-cost savings, and has the crucial advantage of being aligned with
  53 the overall privacy goal *and* with NLnet's funding remit.
  54
  55 ### Summary from the past couple of months
  56
  57 The past few months have seen a *lot* of activity.  The IEEE754 ADD unit
  58 has been completed, both as a finite state machine (FSM) and as a fully
  59 pipelined design, both of which have parameters that allow them to do
  60 FP16, FP32 or FP64.  The DIV unit has been implemented as an FSM, and
  61 will stay that way for now.  MUL has been completed, however needs to
  62 be turned into an FMAC (three operands: multiply and accumulate).
  63
  64 A provisional pipeline API has been developed, which the IEEE754 FPU
  65 is using.  It includes data "funneling" (multiplexing) blocks that allow
  66 for the creation of what Mitch Alsup calls a "concurrent computation unit."
  67 It's basically an array of matched operand latches and result latches
  68 (as input and output, respectively), in front of a single pipeline.
  69 This arrangement allows a batch of operations to be presented to the
  70 CDC6600-style "dependency matrices."
  71
  72 Jacob has been working on a fascinating design: a dynamically partitionable
  73 adder and multiplier unit.  Given that we are doing a vector processing
  74 front-end onto SIMD back-end operations, it makes sense to save gates by
  75 allowing the ADD and MUL units to be able to optionally handle a batch
  76 of 8-bit operations, or half the number of 16-bit operations, or a quarter
  77 of the number of 32-bit operations, or one eighth of the number of 64-bit
  78 operations. In this way, many fewer gates are required than if they
  79 were separate units.  The unit tests demonstrate that the code Jacob
  80 has written provide RISC-V mul, mulh, mulhu and mulhsu functionality.
  81
  82 The augmented 6600 scoreboard took literally six weeks to correctly implement
  83 read-after-write and write-after-read hazards.  It required extraordinary
  84 and excruciating patience to get right.  Adding in write-after-write,
  85 however, only took two days, as the infrastructure to do so had already been
  86 developed.
  87
  88 Currently being implemented is "branch shadowing" - this is not the
  89 same as branch *prediction* - that is a different algorithm which,
  90 when *combined* with "branch shadowing," provides the feature known as
  91 branch *speculation*.  This is the source of a lot of confusion about
  92 out-of-order (OoO) designs in general.  It seems to be assumed that an
  93 OoO design *has* to have branch speculation: it doesn't.  It's just
  94 that, given all the pieces, adding in branch speculation is actually
  95 quite straightforward, and provides such a high-performance increase
  96 that it is hard to justify leaving it out.
  97
  98 One huge surprise came out of a recent discussion with Mitch Alsup.  It
  99 has been assumed all along that turning this design from a single-issue
 100 to multi-issue would be difficult, or require significant gates and latency
 101 to do so.  The "simple" approach to do multi-issue, using the dependency
 102 matrices, would be to analyse a batch of instructions, and if there are
 103 no overlaps (no registers in common), allow that batch to proceed in
 104 parallel.  This is a naive approach.
 105
 106 Mitch pointed out that in his work on the AMD Opteron (the processor
 107 family that AMD had to publish "Intel equivalent" speed numbers for,
 108 because it was so much more efficient and effective than Intel's designs)
 109 each instruction "accumulated" the dependencies of all prior instructions
 110 being issued in the same batch.  This works because read and write
 111 dependencies are *transitive* (whenever a -> b and b -> c then a -> c).
 112
 113 What that means, in practical terms, is that we have a way to create a
 114 design that could, if ramped up, take on the big boys.  To make that
 115 clear: there's no technical barrier that would prevent us from creating
 116 a quad issue (or higher) design.
 117
 118 There is still a heck of a lot to get done.  However, it has to
 119 be said that actually adding an instruction decoder onto the 6600-style
 120 dependency matrices is relatively straightforward, this being RISC, after
 121 all.  It is possible, then, that we may have a subset of functionality
 122 operational far sooner than anticipated.