updates/021_2019dec29_nlnet_grants_approved.mdwn

   1 # NLNet Grants approved: Power ISA under consideration
   2
   3 Across several projects, nearly EUR 400,000 worth of additional funding
   4 applications were put in, and around EUR 200,000 to 250,000 of those have
   5 been approved.  The RISC-V Foundation's continued extreme unethical
   6 actions have led us to consider using Power ISA.
   7
   8 # NLNet Grants
   9
  10 [NLNet](http://nlnet.nl) were first approached eighteen months ago, with
  11 an initial application to develop the core of a privacy-respecting trustable
  12 processor.  Whilst NLNet's primary focus of the past fifteen years has been
  13 software, they have funded reverse-engineering for
  14 [Osmocon BB](https://nlnet.nl/project/sdr-phy/) and for
  15 [OpenBSC](https://nlnet.nl/project/iuh-openbsc/) so are no strangers to
  16 hardware.  The problem with software is: if the hardware cannot be trusted,
  17 then no amount of trustable, open and transparent software will help.
  18
  19 The [additional proposals](https://libre-riscv.org/nlnet_proposals/)
  20 expand on the core, to cover:
  21
  22 * Formal Mathematical correctness proofs for the entire processor, including
  23   the FPU (no more Intel Pentium FPDIV bugs...)
  24 * a special Video Acceleration focus, adding video decode instructions
  25 * an additional 3D Driver based on AMDVLK or MESA
  26 * some funding to be able to properly develop and document ISA standards
  27 * a Wishbone Streaming enhancement to add A/V timecode stamps to Wishbone B4,
  28   and to develop independent libre-licensed peripherals as examples.
  29 * two inter-related proposals to develop Libre Cell Libraries
  30   ([Chips4Makers](http://chips4makers.be)), to be used
  31   by a team at [LIP6.fr](http://lip6.fr)
  32   using the Alliance / Coriolis2 ASIC layout tools.
  33   Additional funding will go to the nmigen team for ASIC improvements and
  34   special integration with Coriolis2.
  35
  36 The goal here is to get to a working, commercially-saleable 180nm single-core
  37 ASIC at around 300 to 350mhz, suitable for use as a high-end Embedded
  38 Controller.  Staf from Chips4Makers will act as the "NDA firebreak" between
  39 us and TSMC.
  40
  41 All of these have been approved by NLNet, and, crucially, the external
  42 independent review process successfully completed for each.  The exact
  43 amounts of each grant is to be confirmed, with each being possible to be
  44 up to the limit of EUR 50,000 for each sub-project.
  45
  46 Part of the process was a little tricky, initially: the independent reviewers
  47 expressed surprise at the amounts being requested for *sub*-tasks when the
  48 initial application was so small.  The reason was very simple: both Jacob
  49 and I have unique low-income circumstances that simply do not need European /
  50 Western style living expenses.  Whereas, when we get to much more specialist
  51 tasks (such as formal mathematical proofs, Video assembly-level drivers,
  52 and so on), these fields are so specialist that finding people who are good
  53 *and* who are able to exist on student or S.E.Asia level funding is just not
  54 practical.
  55
  56 We therefore made sure that the calculations were based around an approximate
  57 EUR 3,000 per month budget per person, bearing in mind that due to NLNet's
  58 International Tax Agreements, this being donations, that's equivalent to a
  59 "wage" of approximately nearly twice that amount (three times if, as a
  60 business, you have to take into consideration Corporation Tax / Employee
  61 Insurance as well).
  62
  63 We therefore need to find people willing to help do the work, and what is
  64 really nice: NLNet will donate money to them for completion of that work!
  65 Therefore, if you've always wanted to work on a 3D processor, its drivers
  66 and its source code, do get in touch.
  67
  68 # PowerPC.
  69
  70 This is a
  71 [long story](http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2019-October/003035.html)
  72 that was picked up by
  73 [Phoronix](https://www.phoronix.com/scan.php?page=news_item&px=Libre-RISC-V-Eyeing-POWER)
  74 before we had a chance to make any kind of real "announcement".  That said:
  75 we're always really grateful to Michael for his coverage of the Libre SoC,
  76 as it always sparks some insightful, useful and engaging discussions.
  77
  78 The summary is this: Libre and Open contributors to RISC-V have been
  79 disregarded for several years.  **Long** before I joined the RISC-V
  80 Mailing lists, it was *well-known* within that small and tightly-knit
  81 community that if you were not associated directly with UCB, you were
  82 basically not welcome.  Caveat: if you signed the NDA-like agreement
  83 which conflicts directly with, for example, the Debian Charter and
  84 the whole purpose of Libre Licenses, then you got a "voice" and you
  85 got access to the closed and secretive RISC-V resources and mailing
  86 lists.
  87
  88 Michael puts it extremely well: I have absolutely no problem with the
  89 ISA itself, it's the abuse of power and the flagrant ignoring and abuse
  90 of basic tenets of Trademark Law that are just completely untenable.
  91 Not only that: one well-paid employee of SiFive has *repeatedly* engaged
  92 in defamation attacks for over eighteen months.  Even raising a formal
  93 complaint through the newly-established relationship with the Linux
  94 Foundation failed to keep that individual under control.  Also adversely
  95 impacted was the newly-established Open Graphics Alliance initiative,
  96 which was independently started by Pixilica back in October,
  97 proposed at SIGGRAPH 2019 and welcomed by world-leading 3D Industry
  98 experts.
  99
 100 At some point you just have to appreciate that to continue to support
 101 an unethical organisation is itself unethical, and thus I made the
 102 decision to reach out to MIPS and Power.  The MIPS website didn't even
 103 work, so I gave up there immediately.  The Open Power Foundation on
 104 the other hand, I was both delighted and surprised to hear back from
 105 a former colleague when I was in Canberra, 20 years ago: Hugh Blemings.
 106
 107 Hugh is extremely knowledgeable, highly intelligent, and completely
 108 understands Libre and Open principles.  We had only 15 minutes to
 109 talk before he had to focus on preparing for the upcoming Open Power
 110 Conference: in that short time, we covered:
 111
 112 * the need for ISANS / ISAMUX "breakout" system.  Hugh even said,
 113   without prompting, that the scheme I quickly described would
 114   allow full software-level ISA emulation and that that was a really
 115   good and necessary thing.  With this **formally** in place as part
 116   of an officially-approved Power ISA Standard, not only could our team
 117   expand the Power ISA in a safe and controlled fashion, so could other
 118   adopters.
 119 * that the core OpenPower members had *already been discussing* how to make
 120   sure that new Libre Teams with a commercial focus could join and not
 121   have any transparency / patent / NDA / royalty / licensing conflicts
 122   of interest.  The only major thing that the other members wanted was
 123   a "P.R. blackout period", right around the time of announcement of
 124   new Standards, which sounds perfectly reasonable to me.
 125 * that IBM will be providing a royalty-free unlimited license grant
 126   for *all* of its patents, as long as firstly the licensees do not
 127   make any effort to assert patents **against** IBM, and secondly,
 128   as long as implementations are fully-compliant with the OpenPower
 129   Standards.
 130 * that there is discussion underway as to the creation and maintenance
 131   of Formal Compliance Test Suites, just as there is today with the
 132   RISC-V ISA.
 133 * that the use of a Certification Mark - not a Service Mark or a Trade Mark -
 134   is the most appropriate thing for ISA Standards.  I mentioned this
 135   only briefly however it takes a lot more than 15 minutes to properly
 136   explain, so I am not going to push it: Hugh is doing so much already.
 137
 138 It was a very busy and positive conversation, where it is clear that
 139 we caught them right at the beginning of the process.  Consequently,
 140 my discussion with Hugh was just at the right time.  Without that,
 141 the existing OpenPower Members might never have really truly believed
 142 that any Libre **Commercial** project would ever in fact come forward
 143 (that the steps that they were taking were purely hypothetical).
 144 Out of the blue (pun intended) I contact Hugh and highlight that no,
 145 it's not hypothetical.
 146
 147 The next step, then, will be to wait until mid-january when people come
 148 back from holiday, and wait for the announcement of the Open Power
 149 License Agreement.  Hugh reassures me that there's nothing spectacularly
 150 controversial in it, and given his long-standing experience of several
 151 decades with the Libre and Open Communities, I cannot think of a reason
 152 why it would not be possible to sign it.  We just have to see.
 153
 154 The timing here with NLNet is just on the edge: we have to create a
 155 full list of milestones and assign a fixed budget to each (then later
 156 subdivide them into sub-tasks under that milestone).  This is a leeeetle
 157 bit challenging when we have not yet reviewed the Open Power Agreement,
 158 however given that the majority of the tasks are ISA-independent, it
 159 will actually work out fine.
 160
 161 The only other major thing: what the heck do we do with the libre-riscv.org
 162 domain?  As you can see on the mailing list decision, we decided to go
 163 with a *userspace* RV64GC dual-ISA front-end.  **userspace** RISC-V POSIX
 164 (Linux / Android) applications will work perfectly well, as will **userspace**
 165 PowerISA POSIX applications, however the **kernel** (supervisor) space will
 166 be entirely PowerISA.
 167
 168 The Video and 3D acceleration opcodes will be **entirely in the Power ISA**.
 169 We are sick and tired of the RISC-V Foundation's blatant mismanagement:
 170 therefore we will comply to the absolute minimal letter with RV64GC for
 171 the benefit of our users, backers and sponsors, however RISC-V and the
 172 RISC-V ISA itself
 173 will no longer receive the benefit of the advancements and innovation
 174 that we have received funding and support to develop.
 175
 176 Therefore: the assembly-code being written by hand for the Video Acceleration
 177 side, as well as the 3D drivers for Kazan and MESA, will "flip" from RV64GC
 178 RISC-V over to the Power ISA, which will be fully 3D accelerated with advanced
 179 Simple-V Vector operations, then return back to userspace RISC-V RV64GC ISA
 180 to continue serving the user application.
 181
 182 Next steps for us include setting up a Foundation under which the processor
 183 can be developed, and to look towards the next major funding step: USD 10m
 184 to 20m.