src/add/multipipe.py

   1 """ Combinatorial Multi-input multiplexer block conforming to Pipeline API
   2 """
   3
   4 from math import log
   5 from nmigen import Signal, Cat, Const, Mux, Module, Array
   6 from nmigen.cli import verilog, rtlil
   7 from nmigen.lib.coding import PriorityEncoder
   8 from nmigen.hdl.rec import Record, Layout
   9
  10 from collections.abc import Sequence
  11
  12 from example_buf_pipe import eq, NextControl, PrevControl, ExampleStage
  13
  14
  15 class MultiInControlBase:
  16     """ Common functions for Pipeline API
  17     """
  18     def __init__(self, in_multi=None, p_len=1):
  19         """ Multi-input Control class.  Conforms to same API as ControlBase...
  20             mostly.  has additional indices to the *multiple* input stages
  21
  22             * p: contains ready/valid to the previous stages PLURAL
  23             * n: contains ready/valid to the next stage
  24
  25             User must also:
  26             * add i_data members to PrevControl and
  27             * add o_data member  to NextControl
  28         """
  29         # set up input and output IO ACK (prev/next ready/valid)
  30         p = []
  31         for i in range(p_len):
  32             p.append(PrevControl(in_multi))
  33         self.p = Array(p)
  34         self.n = NextControl()
  35
  36     def connect_to_next(self, nxt, p_idx=0):
  37         """ helper function to connect to the next stage data/valid/ready.
  38         """
  39         return self.n.connect_to_next(nxt.p[p_idx])
  40
  41     def _connect_in(self, prev, idx=0, prev_idx=None):
  42         """ helper function to connect stage to an input source.  do not
  43             use to connect stage-to-stage!
  44         """
  45         if prev_idx is None:
  46             return self.p[idx]._connect_in(prev.p)
  47         return self.p[idx]._connect_in(prev.p[prev_idx])
  48
  49     def _connect_out(self, nxt):
  50         """ helper function to connect stage to an output source.  do not
  51             use to connect stage-to-stage!
  52         """
  53         if nxt_idx is None:
  54             return self.n._connect_out(nxt.n)
  55         return self.n._connect_out(nxt.n)
  56
  57     def set_input(self, i, idx=0):
  58         """ helper function to set the input data
  59         """
  60         return eq(self.p[idx].i_data, i)
  61
  62     def ports(self):
  63         res = []
  64         for i in range(len(self.p)):
  65             res += [self.p[i].i_valid, self.p[i].o_ready,
  66                     self.p[i].i_data]# XXX need flattening!]
  67         res += [self.n.i_ready, self.n.o_valid,
  68                 self.n.o_data]   # XXX need flattening!]
  69         return res
  70
  71
  72
  73 class MultiOutControlBase:
  74     """ Common functions for Pipeline API
  75     """
  76     def __init__(self, n_len=1):
  77         """ Multi-output Control class
  78
  79             * p: contains ready/valid to the previou stage
  80             * n: contains ready/valid to the next stages PLURAL
  81
  82             User must also:
  83             * add i_data member to PrevControl and
  84             * add o_data members to NextControl
  85         """
  86
  87         # set up input and output IO ACK (prev/next ready/valid)
  88         self.p = PrevControl(in_multi)
  89         for i in range(n_len):
  90             n.append(NextControl())
  91         self.n = Array(n)
  92
  93     def connect_to_next(self, nxt, n_idx=0):
  94         """ helper function to connect to the next stage data/valid/ready.
  95         """
  96         return self.n[n_idx].connect_to_next(nxt.p)
  97
  98     def _connect_in(self, prev, idx=0):
  99         """ helper function to connect stage to an input source.  do not
 100             use to connect stage-to-stage!
 101         """
 102         return self.n[idx]._connect_in(prev.p)
 103
 104     def _connect_out(self, nxt, idx=0, nxt_idx=None):
 105         """ helper function to connect stage to an output source.  do not
 106             use to connect stage-to-stage!
 107         """
 108         if nxt_idx is None:
 109             return self.n[idx]._connect_out(nxt.n)
 110         return self.n[idx]._connect_out(nxt.n[nxt_idx])
 111
 112     def set_input(self, i):
 113         """ helper function to set the input data
 114         """
 115         return eq(self.p.i_data, i)
 116
 117     def ports(self):
 118         res = []
 119         res += [self.p.i_valid, self.p.o_ready,
 120                 self.p.i_data]# XXX need flattening!]
 121         for i in range(len(self.n)):
 122             res += [self.n[i].i_ready, self.n[i].o_valid,
 123                     self.n[i].o_data]   # XXX need flattening!]
 124         return res
 125
 126
 127
 128 class CombMultiOutPipeline(MultiOutControlBase):
 129     """ A multi-input Combinatorial block conforming to the Pipeline API
 130
 131         Attributes:
 132         -----------
 133         p.i_data : StageInput, shaped according to ispec
 134             The pipeline input
 135         p.o_data : StageOutput, shaped according to ospec
 136             The pipeline output
 137         r_data : input_shape according to ispec
 138             A temporary (buffered) copy of a prior (valid) input.
 139             This is HELD if the output is not ready.  It is updated
 140             SYNCHRONOUSLY.
 141     """
 142
 143     def __init__(self, stage, n_len, n_mux):
 144         MultiOutControlBase.__init__(self, n_len=n_len)
 145         self.stage = stage
 146         self.p_mux = p_mux
 147
 148         # set up the input and output data
 149         for i in range(p_len):
 150             self.p[i].i_data = stage.ispec() # input type
 151         self.n.o_data = stage.ospec()
 152
 153     def elaborate(self, platform):
 154         m = Module()
 155
 156         m.submodules += self.p_mux
 157
 158         # need buffer register conforming to *input* spec
 159         r_data = self.stage.ispec() # input type
 160         if hasattr(self.stage, "setup"):
 161             self.stage.setup(m, r_data)
 162
 163         data_valid = []
 164         n_i_readyn = []
 165         n_len = len(self.n)
 166         for i in range(n_len):
 167             data_valid.append(Signal(name="data_valid", reset_less=True))
 168             n_i_readyn.append(Signal(name="n_i_readyn", reset_less=True))
 169         n_i_readyn = Array(n_i_readyn)
 170         data_valid = Array(data_valid)
 171
 172         p_i_valid = Signal(reset_less=True)
 173         m.d.comb += p_i_valid.eq(self.p.i_valid_logic())
 174
 175         mid = self.p_mux.m_id
 176
 177         for i in range(p_len):
 178             m.d.comb += data_valid[i].eq(0)
 179             m.d.comb += n_i_readyn[i].eq(1)
 180             m.d.comb += self.n[i].o_valid.eq(data_valid[i])
 181         m.d.comb += self.p[mid].o_ready.eq(~data_valid[mid] | self.n.i_ready)
 182         m.d.comb += n_i_readyn[mid].eq(~self.n[mid].i_ready & data_valid[mid])
 183         anyvalid = Signal(i, reset_less=True)
 184         av = []
 185         for i in range(p_len):
 186             av.append(~data_valid[i] | self.n[i].i_ready)
 187         anyvalid = Cat(*av)
 188         m.d.comb += self.p.o_ready.eq(anyvalid.bool())
 189         m.d.comb += data_valid[mid].eq(p_i_valid | \
 190                                     (n_i_readyn[mid] & data_valid[mid]))
 191
 192         with m.If(self.p.i_valid & self.p.o_ready):
 193             m.d.comb += eq(r_data, self.p.i_data)
 194         m.d.comb += eq(self.n[mid].o_data, self.stage.process(r_data))
 195
 196         return m
 197
 198
 199 class CombMultiInPipeline(MultiInControlBase):
 200     """ A multi-input Combinatorial block conforming to the Pipeline API
 201
 202         Attributes:
 203         -----------
 204         p.i_data : StageInput, shaped according to ispec
 205             The pipeline input
 206         p.o_data : StageOutput, shaped according to ospec
 207             The pipeline output
 208         r_data : input_shape according to ispec
 209             A temporary (buffered) copy of a prior (valid) input.
 210             This is HELD if the output is not ready.  It is updated
 211             SYNCHRONOUSLY.
 212     """
 213
 214     def __init__(self, stage, p_len, p_mux):
 215         MultiInControlBase.__init__(self, p_len=p_len)
 216         self.stage = stage
 217         self.p_mux = p_mux
 218
 219         # set up the input and output data
 220         for i in range(p_len):
 221             self.p[i].i_data = stage.ispec() # input type
 222         self.n.o_data = stage.ospec()
 223
 224     def elaborate(self, platform):
 225         m = Module()
 226
 227         m.submodules += self.p_mux
 228
 229         # need an array of buffer registers conforming to *input* spec
 230         r_data = []
 231         data_valid = []
 232         p_i_valid = []
 233         n_i_readyn = []
 234         p_len = len(self.p)
 235         for i in range(p_len):
 236             r = self.stage.ispec() # input type
 237             r_data.append(r)
 238             data_valid.append(Signal(name="data_valid", reset_less=True))
 239             p_i_valid.append(Signal(name="p_i_valid", reset_less=True))
 240             n_i_readyn.append(Signal(name="n_i_readyn", reset_less=True))
 241             if hasattr(self.stage, "setup"):
 242                 self.stage.setup(m, r)
 243         if len(r_data) > 1:
 244             r_data = Array(r_data)
 245             p_i_valid = Array(p_i_valid)
 246             n_i_readyn = Array(n_i_readyn)
 247             data_valid = Array(data_valid)
 248
 249         mid = self.p_mux.m_id
 250         for i in range(p_len):
 251             m.d.comb += data_valid[i].eq(0)
 252             m.d.comb += n_i_readyn[i].eq(1)
 253             m.d.comb += p_i_valid[i].eq(0)
 254             m.d.comb += self.p[i].o_ready.eq(0)
 255         m.d.comb += p_i_valid[mid].eq(self.p_mux.active)
 256         m.d.comb += self.p[mid].o_ready.eq(~data_valid[mid] | self.n.i_ready)
 257         m.d.comb += n_i_readyn[mid].eq(~self.n.i_ready & data_valid[mid])
 258         anyvalid = Signal(i, reset_less=True)
 259         av = []
 260         for i in range(p_len):
 261             av.append(data_valid[i])
 262         anyvalid = Cat(*av)
 263         m.d.comb += self.n.o_valid.eq(anyvalid.bool())
 264         m.d.comb += data_valid[mid].eq(p_i_valid[mid] | \
 265                                     (n_i_readyn[mid] & data_valid[mid]))
 266
 267         for i in range(p_len):
 268             vr = Signal(reset_less=True)
 269             m.d.comb += vr.eq(self.p[i].i_valid & self.p[i].o_ready)
 270             with m.If(vr):
 271                 m.d.comb += eq(r_data[i], self.p[i].i_data)
 272
 273         m.d.comb += eq(self.n.o_data, self.stage.process(r_data[mid]))
 274
 275         return m
 276
 277
 278 class InputPriorityArbiter:
 279     def __init__(self, pipe, num_rows):
 280         self.pipe = pipe
 281         self.num_rows = num_rows
 282         self.mmax = int(log(self.num_rows) / log(2))
 283         self.m_id = Signal(self.mmax, reset_less=True) # multiplex id
 284         self.active = Signal(reset_less=True)
 285
 286     def elaborate(self, platform):
 287         m = Module()
 288
 289         assert len(self.pipe.p) == self.num_rows, \
 290                 "must declare input to be same size"
 291         pe = PriorityEncoder(self.num_rows)
 292         m.submodules.selector = pe
 293
 294         # connect priority encoder
 295         in_ready = []
 296         for i in range(self.num_rows):
 297             p_i_valid = Signal(reset_less=True)
 298             m.d.comb += p_i_valid.eq(self.pipe.p[i].i_valid_logic())
 299             in_ready.append(p_i_valid)
 300         m.d.comb += pe.i.eq(Cat(*in_ready)) # array of input "valids"
 301         m.d.comb += self.active.eq(~pe.n)   # encoder active (one input valid)
 302         m.d.comb += self.m_id.eq(pe.o)       # output one active input
 303
 304         return m
 305
 306     def ports(self):
 307         return [self.m_id, self.active]
 308
 309
 310
 311 class ExamplePipeline(CombMultiInPipeline):
 312     """ an example of how to use the combinatorial pipeline.
 313     """
 314
 315     def __init__(self, p_len=2):
 316         p_mux = InputPriorityArbiter(self, p_len)
 317         CombMultiInPipeline.__init__(self, ExampleStage, p_len, p_mux)
 318
 319
 320 if __name__ == '__main__':
 321
 322     dut = ExamplePipeline()
 323     vl = rtlil.convert(dut, ports=dut.ports())
 324     with open("test_combpipe.il", "w") as f:
 325         f.write(vl)