src/add/nmigen_add_experiment.py

   1 # IEEE Floating Point Adder (Single Precision)
   2 # Copyright (C) Jonathan P Dawson 2013
   3 # 2013-12-12
   4
   5 from nmigen import Module, Signal, Cat, Mux, Array, Const
   6 from nmigen.lib.coding import PriorityEncoder
   7 from nmigen.cli import main, verilog
   8 from math import log
   9
  10 from fpbase import FPNumIn, FPNumOut, FPOp, Overflow, FPBase, FPNumBase
  11 from fpbase import MultiShiftRMerge, Trigger
  12 from example_buf_pipe import StageChain, UnbufferedPipeline
  13 #from fpbase import FPNumShiftMultiRight
  14
  15
  16 class FPState(FPBase):
  17     def __init__(self, state_from):
  18         self.state_from = state_from
  19
  20     def set_inputs(self, inputs):
  21         self.inputs = inputs
  22         for k,v in inputs.items():
  23             setattr(self, k, v)
  24
  25     def set_outputs(self, outputs):
  26         self.outputs = outputs
  27         for k,v in outputs.items():
  28             setattr(self, k, v)
  29
  30
  31 class FPGetSyncOpsMod:
  32     def __init__(self, width, num_ops=2):
  33         self.width = width
  34         self.num_ops = num_ops
  35         inops = []
  36         outops = []
  37         for i in range(num_ops):
  38             inops.append(Signal(width, reset_less=True))
  39             outops.append(Signal(width, reset_less=True))
  40         self.in_op = inops
  41         self.out_op = outops
  42         self.stb = Signal(num_ops)
  43         self.ack = Signal()
  44         self.ready = Signal(reset_less=True)
  45         self.out_decode = Signal(reset_less=True)
  46
  47     def elaborate(self, platform):
  48         m = Module()
  49         m.d.comb += self.ready.eq(self.stb == Const(-1, (self.num_ops, False)))
  50         m.d.comb += self.out_decode.eq(self.ack & self.ready)
  51         with m.If(self.out_decode):
  52             for i in range(self.num_ops):
  53                 m.d.comb += [
  54                         self.out_op[i].eq(self.in_op[i]),
  55                 ]
  56         return m
  57
  58     def ports(self):
  59         return self.in_op + self.out_op + [self.stb, self.ack]
  60
  61
  62 class FPOps(Trigger):
  63     def __init__(self, width, num_ops):
  64         Trigger.__init__(self)
  65         self.width = width
  66         self.num_ops = num_ops
  67
  68         res = []
  69         for i in range(num_ops):
  70             res.append(Signal(width))
  71         self.v  = Array(res)
  72
  73     def ports(self):
  74         res = []
  75         for i in range(self.num_ops):
  76             res.append(self.v[i])
  77         res.append(self.ack)
  78         res.append(self.stb)
  79         return res
  80
  81
  82 class InputGroup:
  83     def __init__(self, width, num_ops=2, num_rows=4):
  84         self.width = width
  85         self.num_ops = num_ops
  86         self.num_rows = num_rows
  87         self.mmax = int(log(self.num_rows) / log(2))
  88         self.rs = []
  89         self.mid = Signal(self.mmax, reset_less=True) # multiplex id
  90         for i in range(num_rows):
  91             self.rs.append(FPGetSyncOpsMod(width, num_ops))
  92         self.rs = Array(self.rs)
  93
  94         self.out_op = FPOps(width, num_ops)
  95
  96     def elaborate(self, platform):
  97         m = Module()
  98
  99         pe = PriorityEncoder(self.num_rows)
 100         m.submodules.selector = pe
 101         m.submodules.out_op = self.out_op
 102         m.submodules += self.rs
 103
 104         # connect priority encoder
 105         in_ready = []
 106         for i in range(self.num_rows):
 107             in_ready.append(self.rs[i].ready)
 108         m.d.comb += pe.i.eq(Cat(*in_ready))
 109
 110         active = Signal(reset_less=True)
 111         out_en = Signal(reset_less=True)
 112         m.d.comb += active.eq(~pe.n) # encoder active
 113         m.d.comb += out_en.eq(active & self.out_op.trigger)
 114
 115         # encoder active: ack relevant input, record MID, pass output
 116         with m.If(out_en):
 117             rs = self.rs[pe.o]
 118             m.d.sync += self.mid.eq(pe.o)
 119             m.d.sync += rs.ack.eq(0)
 120             m.d.sync += self.out_op.stb.eq(0)
 121             for j in range(self.num_ops):
 122                 m.d.sync += self.out_op.v[j].eq(rs.out_op[j])
 123         with m.Else():
 124             m.d.sync += self.out_op.stb.eq(1)
 125             # acks all default to zero
 126             for i in range(self.num_rows):
 127                 m.d.sync += self.rs[i].ack.eq(1)
 128
 129         return m
 130
 131     def ports(self):
 132         res = []
 133         for i in range(self.num_rows):
 134             inop = self.rs[i]
 135             res += inop.in_op + [inop.stb]
 136         return self.out_op.ports() + res + [self.mid]
 137
 138
 139 class FPGetOpMod:
 140     def __init__(self, width):
 141         self.in_op = FPOp(width)
 142         self.out_op = Signal(width)
 143         self.out_decode = Signal(reset_less=True)
 144
 145     def elaborate(self, platform):
 146         m = Module()
 147         m.d.comb += self.out_decode.eq((self.in_op.ack) & (self.in_op.stb))
 148         m.submodules.get_op_in = self.in_op
 149         #m.submodules.get_op_out = self.out_op
 150         with m.If(self.out_decode):
 151             m.d.comb += [
 152                 self.out_op.eq(self.in_op.v),
 153             ]
 154         return m
 155
 156
 157 class FPGetOp(FPState):
 158     """ gets operand
 159     """
 160
 161     def __init__(self, in_state, out_state, in_op, width):
 162         FPState.__init__(self, in_state)
 163         self.out_state = out_state
 164         self.mod = FPGetOpMod(width)
 165         self.in_op = in_op
 166         self.out_op = Signal(width)
 167         self.out_decode = Signal(reset_less=True)
 168
 169     def setup(self, m, in_op):
 170         """ links module to inputs and outputs
 171         """
 172         setattr(m.submodules, self.state_from, self.mod)
 173         m.d.comb += self.mod.in_op.eq(in_op)
 174         m.d.comb += self.out_decode.eq(self.mod.out_decode)
 175
 176     def action(self, m):
 177         with m.If(self.out_decode):
 178             m.next = self.out_state
 179             m.d.sync += [
 180                 self.in_op.ack.eq(0),
 181                 self.out_op.eq(self.mod.out_op)
 182             ]
 183         with m.Else():
 184             m.d.sync += self.in_op.ack.eq(1)
 185
 186
 187 class FPGet2OpMod(Trigger):
 188     def __init__(self, width, id_wid):
 189         Trigger.__init__(self)
 190         self.width = width
 191         self.id_wid = id_wid
 192         self.i = self.ispec()
 193         self.o = self.ospec()
 194
 195     def ispec(self):
 196         return FPADDBaseData(self.width, self.id_wid)
 197
 198     def ospec(self):
 199         return FPNumBase2Ops(self.width, self.id_wid)
 200
 201     def elaborate(self, platform):
 202         m = Trigger.elaborate(self, platform)
 203         m.submodules.get_op1_out = self.o.a
 204         m.submodules.get_op2_out = self.o.b
 205         out_op1 = FPNumIn(None, self.width)
 206         out_op2 = FPNumIn(None, self.width)
 207         with m.If(self.trigger):
 208             m.d.comb += [
 209                 out_op1.decode(self.i.a),
 210                 out_op2.decode(self.i.b),
 211                 self.o.a.eq(out_op1),
 212                 self.o.b.eq(out_op2),
 213                 self.o.mid.eq(self.i.mid)
 214             ]
 215         return m
 216
 217
 218 class FPGet2Op(FPState):
 219     """ gets operands
 220     """
 221
 222     def __init__(self, in_state, out_state, width, id_wid):
 223         FPState.__init__(self, in_state)
 224         self.out_state = out_state
 225         self.mod = FPGet2OpMod(width, id_wid)
 226         self.o = self.mod.ospec()
 227         self.in_stb = Signal(reset_less=True)
 228         self.out_ack = Signal(reset_less=True)
 229         self.out_decode = Signal(reset_less=True)
 230
 231     def setup(self, m, i, in_stb, in_ack):
 232         """ links module to inputs and outputs
 233         """
 234         m.submodules.get_ops = self.mod
 235         m.d.comb += self.mod.i.eq(i)
 236         m.d.comb += self.mod.stb.eq(in_stb)
 237         m.d.comb += self.out_ack.eq(self.mod.ack)
 238         m.d.comb += self.out_decode.eq(self.mod.trigger)
 239         m.d.comb += in_ack.eq(self.mod.ack)
 240
 241     def action(self, m):
 242         with m.If(self.out_decode):
 243             m.next = self.out_state
 244             m.d.sync += [
 245                 self.mod.ack.eq(0),
 246                 self.o.eq(self.mod.o),
 247             ]
 248         with m.Else():
 249             m.d.sync += self.mod.ack.eq(1)
 250
 251
 252 class FPNumBase2Ops:
 253
 254     def __init__(self, width, id_wid, m_extra=True):
 255         self.a = FPNumBase(width, m_extra)
 256         self.b = FPNumBase(width, m_extra)
 257         self.mid = Signal(id_wid, reset_less=True)
 258
 259     def eq(self, i):
 260         return [self.a.eq(i.a), self.b.eq(i.b), self.mid.eq(i.mid)]
 261
 262
 263 class FPSCData:
 264
 265     def __init__(self, width, id_wid):
 266         self.a = FPNumBase(width, True)
 267         self.b = FPNumBase(width, True)
 268         self.z = FPNumOut(width, False)
 269         self.oz = Signal(width, reset_less=True)
 270         self.out_do_z = Signal(reset_less=True)
 271         self.mid = Signal(id_wid, reset_less=True)
 272
 273     def eq(self, i):
 274         return [self.z.eq(i.z), self.out_do_z.eq(i.out_do_z), self.oz.eq(i.oz),
 275                 self.a.eq(i.a), self.b.eq(i.b), self.mid.eq(i.mid)]
 276
 277
 278 class FPAddSpecialCasesMod:
 279     """ special cases: NaNs, infs, zeros, denormalised
 280         NOTE: some of these are unique to add.  see "Special Operations"
 281         https://steve.hollasch.net/cgindex/coding/ieeefloat.html
 282     """
 283
 284     def __init__(self, width, id_wid):
 285         self.width = width
 286         self.id_wid = id_wid
 287         self.i = self.ispec()
 288         self.o = self.ospec()
 289
 290     def ispec(self):
 291         return FPNumBase2Ops(self.width, self.id_wid)
 292
 293     def ospec(self):
 294         return FPSCData(self.width, self.id_wid)
 295
 296     def setup(self, m, i):
 297         """ links module to inputs and outputs
 298         """
 299         m.submodules.specialcases = self
 300         m.d.comb += self.i.eq(i)
 301
 302     def elaborate(self, platform):
 303         m = Module()
 304
 305         m.submodules.sc_in_a = self.i.a
 306         m.submodules.sc_in_b = self.i.b
 307         m.submodules.sc_out_z = self.o.z
 308
 309         s_nomatch = Signal()
 310         m.d.comb += s_nomatch.eq(self.i.a.s != self.i.b.s)
 311
 312         m_match = Signal()
 313         m.d.comb += m_match.eq(self.i.a.m == self.i.b.m)
 314
 315         # if a is NaN or b is NaN return NaN
 316         with m.If(self.i.a.is_nan | self.i.b.is_nan):
 317             m.d.comb += self.o.out_do_z.eq(1)
 318             m.d.comb += self.o.z.nan(0)
 319
 320         # XXX WEIRDNESS for FP16 non-canonical NaN handling
 321         # under review
 322
 323         ## if a is zero and b is NaN return -b
 324         #with m.If(a.is_zero & (a.s==0) & b.is_nan):
 325         #    m.d.comb += self.o.out_do_z.eq(1)
 326         #    m.d.comb += z.create(b.s, b.e, Cat(b.m[3:-2], ~b.m[0]))
 327
 328         ## if b is zero and a is NaN return -a
 329         #with m.Elif(b.is_zero & (b.s==0) & a.is_nan):
 330         #    m.d.comb += self.o.out_do_z.eq(1)
 331         #    m.d.comb += z.create(a.s, a.e, Cat(a.m[3:-2], ~a.m[0]))
 332
 333         ## if a is -zero and b is NaN return -b
 334         #with m.Elif(a.is_zero & (a.s==1) & b.is_nan):
 335         #    m.d.comb += self.o.out_do_z.eq(1)
 336         #    m.d.comb += z.create(a.s & b.s, b.e, Cat(b.m[3:-2], 1))
 337
 338         ## if b is -zero and a is NaN return -a
 339         #with m.Elif(b.is_zero & (b.s==1) & a.is_nan):
 340         #    m.d.comb += self.o.out_do_z.eq(1)
 341         #    m.d.comb += z.create(a.s & b.s, a.e, Cat(a.m[3:-2], 1))
 342
 343         # if a is inf return inf (or NaN)
 344         with m.Elif(self.i.a.is_inf):
 345             m.d.comb += self.o.out_do_z.eq(1)
 346             m.d.comb += self.o.z.inf(self.i.a.s)
 347             # if a is inf and signs don't match return NaN
 348             with m.If(self.i.b.exp_128 & s_nomatch):
 349                 m.d.comb += self.o.z.nan(0)
 350
 351         # if b is inf return inf
 352         with m.Elif(self.i.b.is_inf):
 353             m.d.comb += self.o.out_do_z.eq(1)
 354             m.d.comb += self.o.z.inf(self.i.b.s)
 355
 356         # if a is zero and b zero return signed-a/b
 357         with m.Elif(self.i.a.is_zero & self.i.b.is_zero):
 358             m.d.comb += self.o.out_do_z.eq(1)
 359             m.d.comb += self.o.z.create(self.i.a.s & self.i.b.s,
 360                                           self.i.b.e,
 361                                           self.i.b.m[3:-1])
 362
 363         # if a is zero return b
 364         with m.Elif(self.i.a.is_zero):
 365             m.d.comb += self.o.out_do_z.eq(1)
 366             m.d.comb += self.o.z.create(self.i.b.s, self.i.b.e,
 367                                       self.i.b.m[3:-1])
 368
 369         # if b is zero return a
 370         with m.Elif(self.i.b.is_zero):
 371             m.d.comb += self.o.out_do_z.eq(1)
 372             m.d.comb += self.o.z.create(self.i.a.s, self.i.a.e,
 373                                       self.i.a.m[3:-1])
 374
 375         # if a equal to -b return zero (+ve zero)
 376         with m.Elif(s_nomatch & m_match & (self.i.a.e == self.i.b.e)):
 377             m.d.comb += self.o.out_do_z.eq(1)
 378             m.d.comb += self.o.z.zero(0)
 379
 380         # Denormalised Number checks next, so pass a/b data through
 381         with m.Else():
 382             m.d.comb += self.o.out_do_z.eq(0)
 383             m.d.comb += self.o.a.eq(self.i.a)
 384             m.d.comb += self.o.b.eq(self.i.b)
 385
 386         m.d.comb += self.o.oz.eq(self.o.z.v)
 387         m.d.comb += self.o.mid.eq(self.i.mid)
 388
 389         return m
 390
 391
 392 class FPID:
 393     def __init__(self, id_wid):
 394         self.id_wid = id_wid
 395         if self.id_wid:
 396             self.in_mid = Signal(id_wid, reset_less=True)
 397             self.out_mid = Signal(id_wid, reset_less=True)
 398         else:
 399             self.in_mid = None
 400             self.out_mid = None
 401
 402     def idsync(self, m):
 403         if self.id_wid is not None:
 404             m.d.sync += self.out_mid.eq(self.in_mid)
 405
 406
 407 class FPAddSpecialCases(FPState):
 408     """ special cases: NaNs, infs, zeros, denormalised
 409         NOTE: some of these are unique to add.  see "Special Operations"
 410         https://steve.hollasch.net/cgindex/coding/ieeefloat.html
 411     """
 412
 413     def __init__(self, width, id_wid):
 414         FPState.__init__(self, "special_cases")
 415         self.mod = FPAddSpecialCasesMod(width)
 416         self.out_z = self.mod.ospec()
 417         self.out_do_z = Signal(reset_less=True)
 418
 419     def setup(self, m, i):
 420         """ links module to inputs and outputs
 421         """
 422         self.mod.setup(m, i, self.out_do_z)
 423         m.d.sync += self.out_z.v.eq(self.mod.out_z.v) # only take the output
 424         m.d.sync += self.out_z.mid.eq(self.mod.o.mid)  # (and mid)
 425
 426     def action(self, m):
 427         self.idsync(m)
 428         with m.If(self.out_do_z):
 429             m.next = "put_z"
 430         with m.Else():
 431             m.next = "denormalise"
 432
 433
 434 class FPAddSpecialCasesDeNorm(FPState):
 435     """ special cases: NaNs, infs, zeros, denormalised
 436         NOTE: some of these are unique to add.  see "Special Operations"
 437         https://steve.hollasch.net/cgindex/coding/ieeefloat.html
 438     """
 439
 440     def __init__(self, width, id_wid):
 441         FPState.__init__(self, "special_cases")
 442         self.smod = FPAddSpecialCasesMod(width, id_wid)
 443         self.out_z = self.smod.ospec()
 444         self.out_do_z = Signal(reset_less=True)
 445
 446         self.dmod = FPAddDeNormMod(width, id_wid)
 447         self.o = self.dmod.ospec()
 448
 449     def setup(self, m, i):
 450         """ links module to inputs and outputs
 451         """
 452         self.smod.setup(m, i)
 453         self.dmod.setup(m, self.smod.o)
 454         m.d.comb += self.out_do_z.eq(self.smod.o.out_do_z)
 455
 456         # out_do_z=True
 457         m.d.sync += self.out_z.z.v.eq(self.smod.o.z.v) # only take output
 458         m.d.sync += self.out_z.mid.eq(self.smod.o.mid)  # (and mid)
 459         # out_do_z=False
 460         m.d.sync += self.o.eq(self.dmod.o)
 461
 462     def action(self, m):
 463         #with m.If(self.out_do_z):
 464         #    m.next = "put_z"
 465         #with m.Else():
 466             m.next = "align"
 467
 468
 469 class FPAddDeNormMod(FPState):
 470
 471     def __init__(self, width, id_wid):
 472         self.width = width
 473         self.id_wid = id_wid
 474         self.i = self.ispec()
 475         self.o = self.ospec()
 476
 477     def ispec(self):
 478         return FPSCData(self.width, self.id_wid)
 479
 480     def ospec(self):
 481         return FPSCData(self.width, self.id_wid)
 482
 483     def setup(self, m, i):
 484         """ links module to inputs and outputs
 485         """
 486         m.submodules.denormalise = self
 487         m.d.comb += self.i.eq(i)
 488
 489     def elaborate(self, platform):
 490         m = Module()
 491         m.submodules.denorm_in_a = self.i.a
 492         m.submodules.denorm_in_b = self.i.b
 493         m.submodules.denorm_out_a = self.o.a
 494         m.submodules.denorm_out_b = self.o.b
 495
 496         with m.If(~self.i.out_do_z):
 497             # XXX hmmm, don't like repeating identical code
 498             m.d.comb += self.o.a.eq(self.i.a)
 499             with m.If(self.i.a.exp_n127):
 500                 m.d.comb += self.o.a.e.eq(self.i.a.N126) # limit a exponent
 501             with m.Else():
 502                 m.d.comb += self.o.a.m[-1].eq(1) # set top mantissa bit
 503
 504             m.d.comb += self.o.b.eq(self.i.b)
 505             with m.If(self.i.b.exp_n127):
 506                 m.d.comb += self.o.b.e.eq(self.i.b.N126) # limit a exponent
 507             with m.Else():
 508                 m.d.comb += self.o.b.m[-1].eq(1) # set top mantissa bit
 509
 510         m.d.comb += self.o.mid.eq(self.i.mid)
 511         m.d.comb += self.o.z.eq(self.i.z)
 512         m.d.comb += self.o.out_do_z.eq(self.i.out_do_z)
 513         m.d.comb += self.o.oz.eq(self.i.oz)
 514
 515         return m
 516
 517
 518 class FPAddDeNorm(FPState):
 519
 520     def __init__(self, width, id_wid):
 521         FPState.__init__(self, "denormalise")
 522         self.mod = FPAddDeNormMod(width)
 523         self.out_a = FPNumBase(width)
 524         self.out_b = FPNumBase(width)
 525
 526     def setup(self, m, i):
 527         """ links module to inputs and outputs
 528         """
 529         self.mod.setup(m, i)
 530
 531         m.d.sync += self.out_a.eq(self.mod.out_a)
 532         m.d.sync += self.out_b.eq(self.mod.out_b)
 533
 534     def action(self, m):
 535         # Denormalised Number checks
 536         m.next = "align"
 537
 538
 539 class FPAddAlignMultiMod(FPState):
 540
 541     def __init__(self, width):
 542         self.in_a = FPNumBase(width)
 543         self.in_b = FPNumBase(width)
 544         self.out_a = FPNumIn(None, width)
 545         self.out_b = FPNumIn(None, width)
 546         self.exp_eq = Signal(reset_less=True)
 547
 548     def elaborate(self, platform):
 549         # This one however (single-cycle) will do the shift
 550         # in one go.
 551
 552         m = Module()
 553
 554         m.submodules.align_in_a = self.in_a
 555         m.submodules.align_in_b = self.in_b
 556         m.submodules.align_out_a = self.out_a
 557         m.submodules.align_out_b = self.out_b
 558
 559         # NOTE: this does *not* do single-cycle multi-shifting,
 560         #       it *STAYS* in the align state until exponents match
 561
 562         # exponent of a greater than b: shift b down
 563         m.d.comb += self.exp_eq.eq(0)
 564         m.d.comb += self.out_a.eq(self.in_a)
 565         m.d.comb += self.out_b.eq(self.in_b)
 566         agtb = Signal(reset_less=True)
 567         altb = Signal(reset_less=True)
 568         m.d.comb += agtb.eq(self.in_a.e > self.in_b.e)
 569         m.d.comb += altb.eq(self.in_a.e < self.in_b.e)
 570         with m.If(agtb):
 571             m.d.comb += self.out_b.shift_down(self.in_b)
 572         # exponent of b greater than a: shift a down
 573         with m.Elif(altb):
 574             m.d.comb += self.out_a.shift_down(self.in_a)
 575         # exponents equal: move to next stage.
 576         with m.Else():
 577             m.d.comb += self.exp_eq.eq(1)
 578         return m
 579
 580
 581 class FPAddAlignMulti(FPState):
 582
 583     def __init__(self, width, id_wid):
 584         FPState.__init__(self, "align")
 585         self.mod = FPAddAlignMultiMod(width)
 586         self.out_a = FPNumIn(None, width)
 587         self.out_b = FPNumIn(None, width)
 588         self.exp_eq = Signal(reset_less=True)
 589
 590     def setup(self, m, in_a, in_b):
 591         """ links module to inputs and outputs
 592         """
 593         m.submodules.align = self.mod
 594         m.d.comb += self.mod.in_a.eq(in_a)
 595         m.d.comb += self.mod.in_b.eq(in_b)
 596         #m.d.comb += self.out_a.eq(self.mod.out_a)
 597         #m.d.comb += self.out_b.eq(self.mod.out_b)
 598         m.d.comb += self.exp_eq.eq(self.mod.exp_eq)
 599         m.d.sync += self.out_a.eq(self.mod.out_a)
 600         m.d.sync += self.out_b.eq(self.mod.out_b)
 601
 602     def action(self, m):
 603         with m.If(self.exp_eq):
 604             m.next = "add_0"
 605
 606
 607 class FPNumIn2Ops:
 608
 609     def __init__(self, width, id_wid):
 610         self.a = FPNumIn(None, width)
 611         self.b = FPNumIn(None, width)
 612         self.z = FPNumOut(width, False)
 613         self.out_do_z = Signal(reset_less=True)
 614         self.oz = Signal(width, reset_less=True)
 615         self.mid = Signal(id_wid, reset_less=True)
 616
 617     def eq(self, i):
 618         return [self.z.eq(i.z), self.out_do_z.eq(i.out_do_z), self.oz.eq(i.oz),
 619                 self.a.eq(i.a), self.b.eq(i.b), self.mid.eq(i.mid)]
 620
 621
 622 class FPAddAlignSingleMod:
 623
 624     def __init__(self, width, id_wid):
 625         self.width = width
 626         self.id_wid = id_wid
 627         self.i = self.ispec()
 628         self.o = self.ospec()
 629
 630     def ispec(self):
 631         return FPSCData(self.width, self.id_wid)
 632
 633     def ospec(self):
 634         return FPNumIn2Ops(self.width, self.id_wid)
 635
 636     def process(self, i):
 637         return self.o
 638
 639     def setup(self, m, i):
 640         """ links module to inputs and outputs
 641         """
 642         m.submodules.align = self
 643         m.d.comb += self.i.eq(i)
 644
 645     def elaborate(self, platform):
 646         """ Aligns A against B or B against A, depending on which has the
 647             greater exponent.  This is done in a *single* cycle using
 648             variable-width bit-shift
 649
 650             the shifter used here is quite expensive in terms of gates.
 651             Mux A or B in (and out) into temporaries, as only one of them
 652             needs to be aligned against the other
 653         """
 654         m = Module()
 655
 656         m.submodules.align_in_a = self.i.a
 657         m.submodules.align_in_b = self.i.b
 658         m.submodules.align_out_a = self.o.a
 659         m.submodules.align_out_b = self.o.b
 660
 661         # temporary (muxed) input and output to be shifted
 662         t_inp = FPNumBase(self.width)
 663         t_out = FPNumIn(None, self.width)
 664         espec = (len(self.i.a.e), True)
 665         msr = MultiShiftRMerge(self.i.a.m_width, espec)
 666         m.submodules.align_t_in = t_inp
 667         m.submodules.align_t_out = t_out
 668         m.submodules.multishift_r = msr
 669
 670         ediff = Signal(espec, reset_less=True)
 671         ediffr = Signal(espec, reset_less=True)
 672         tdiff = Signal(espec, reset_less=True)
 673         elz = Signal(reset_less=True)
 674         egz = Signal(reset_less=True)
 675
 676         # connect multi-shifter to t_inp/out mantissa (and tdiff)
 677         m.d.comb += msr.inp.eq(t_inp.m)
 678         m.d.comb += msr.diff.eq(tdiff)
 679         m.d.comb += t_out.m.eq(msr.m)
 680         m.d.comb += t_out.e.eq(t_inp.e + tdiff)
 681         m.d.comb += t_out.s.eq(t_inp.s)
 682
 683         m.d.comb += ediff.eq(self.i.a.e - self.i.b.e)
 684         m.d.comb += ediffr.eq(self.i.b.e - self.i.a.e)
 685         m.d.comb += elz.eq(self.i.a.e < self.i.b.e)
 686         m.d.comb += egz.eq(self.i.a.e > self.i.b.e)
 687
 688         # default: A-exp == B-exp, A and B untouched (fall through)
 689         m.d.comb += self.o.a.eq(self.i.a)
 690         m.d.comb += self.o.b.eq(self.i.b)
 691         # only one shifter (muxed)
 692         #m.d.comb += t_out.shift_down_multi(tdiff, t_inp)
 693         # exponent of a greater than b: shift b down
 694         with m.If(~self.i.out_do_z):
 695             with m.If(egz):
 696                 m.d.comb += [t_inp.eq(self.i.b),
 697                              tdiff.eq(ediff),
 698                              self.o.b.eq(t_out),
 699                              self.o.b.s.eq(self.i.b.s), # whoops forgot sign
 700                             ]
 701             # exponent of b greater than a: shift a down
 702             with m.Elif(elz):
 703                 m.d.comb += [t_inp.eq(self.i.a),
 704                              tdiff.eq(ediffr),
 705                              self.o.a.eq(t_out),
 706                              self.o.a.s.eq(self.i.a.s), # whoops forgot sign
 707                             ]
 708
 709         m.d.comb += self.o.mid.eq(self.i.mid)
 710         m.d.comb += self.o.z.eq(self.i.z)
 711         m.d.comb += self.o.out_do_z.eq(self.i.out_do_z)
 712         m.d.comb += self.o.oz.eq(self.i.oz)
 713
 714         return m
 715
 716
 717 class FPAddAlignSingle(FPState):
 718
 719     def __init__(self, width, id_wid):
 720         FPState.__init__(self, "align")
 721         self.mod = FPAddAlignSingleMod(width, id_wid)
 722         self.out_a = FPNumIn(None, width)
 723         self.out_b = FPNumIn(None, width)
 724
 725     def setup(self, m, i):
 726         """ links module to inputs and outputs
 727         """
 728         self.mod.setup(m, i)
 729
 730         # NOTE: could be done as comb
 731         m.d.sync += self.out_a.eq(self.mod.out_a)
 732         m.d.sync += self.out_b.eq(self.mod.out_b)
 733
 734     def action(self, m):
 735         m.next = "add_0"
 736
 737
 738 class FPAddAlignSingleAdd(FPState):
 739
 740     def __init__(self, width, id_wid):
 741         FPState.__init__(self, "align")
 742         self.width = width
 743         self.id_wid = id_wid
 744         self.a1o = self.ospec()
 745
 746     def ispec(self):
 747         return FPNumBase2Ops(self.width, self.id_wid) # AlignSingle ispec
 748
 749     def ospec(self):
 750         return FPAddStage1Data(self.width, self.id_wid) # AddStage1 ospec
 751
 752     def setup(self, m, i):
 753         """ links module to inputs and outputs
 754         """
 755
 756         # chain AddAlignSingle, AddStage0 and AddStage1
 757         mod = FPAddAlignSingleMod(self.width, self.id_wid)
 758         a0mod = FPAddStage0Mod(self.width, self.id_wid)
 759         a1mod = FPAddStage1Mod(self.width, self.id_wid)
 760
 761         chain = StageChain([mod, a0mod, a1mod])
 762         chain.setup(m, i)
 763
 764         m.d.sync += self.a1o.eq(a1mod.o)
 765
 766     def action(self, m):
 767         m.next = "normalise_1"
 768
 769
 770 class FPAddStage0Data:
 771
 772     def __init__(self, width, id_wid):
 773         self.z = FPNumBase(width, False)
 774         self.out_do_z = Signal(reset_less=True)
 775         self.oz = Signal(width, reset_less=True)
 776         self.tot = Signal(self.z.m_width + 4, reset_less=True)
 777         self.mid = Signal(id_wid, reset_less=True)
 778
 779     def eq(self, i):
 780         return [self.z.eq(i.z), self.out_do_z.eq(i.out_do_z), self.oz.eq(i.oz),
 781                 self.tot.eq(i.tot), self.mid.eq(i.mid)]
 782
 783
 784 class FPAddStage0Mod:
 785
 786     def __init__(self, width, id_wid):
 787         self.width = width
 788         self.id_wid = id_wid
 789         self.i = self.ispec()
 790         self.o = self.ospec()
 791
 792     def ispec(self):
 793         return FPSCData(self.width, self.id_wid)
 794
 795     def ospec(self):
 796         return FPAddStage0Data(self.width, self.id_wid)
 797
 798     def process(self, i):
 799         return self.o
 800
 801     def setup(self, m, i):
 802         """ links module to inputs and outputs
 803         """
 804         m.submodules.add0 = self
 805         m.d.comb += self.i.eq(i)
 806
 807     def elaborate(self, platform):
 808         m = Module()
 809         m.submodules.add0_in_a = self.i.a
 810         m.submodules.add0_in_b = self.i.b
 811         m.submodules.add0_out_z = self.o.z
 812
 813         # store intermediate tests (and zero-extended mantissas)
 814         seq = Signal(reset_less=True)
 815         mge = Signal(reset_less=True)
 816         am0 = Signal(len(self.i.a.m)+1, reset_less=True)
 817         bm0 = Signal(len(self.i.b.m)+1, reset_less=True)
 818         m.d.comb += [seq.eq(self.i.a.s == self.i.b.s),
 819                      mge.eq(self.i.a.m >= self.i.b.m),
 820                      am0.eq(Cat(self.i.a.m, 0)),
 821                      bm0.eq(Cat(self.i.b.m, 0))
 822                     ]
 823         # same-sign (both negative or both positive) add mantissas
 824         with m.If(~self.i.out_do_z):
 825             m.d.comb += self.o.z.e.eq(self.i.a.e)
 826             with m.If(seq):
 827                 m.d.comb += [
 828                     self.o.tot.eq(am0 + bm0),
 829                     self.o.z.s.eq(self.i.a.s)
 830                 ]
 831             # a mantissa greater than b, use a
 832             with m.Elif(mge):
 833                 m.d.comb += [
 834                     self.o.tot.eq(am0 - bm0),
 835                     self.o.z.s.eq(self.i.a.s)
 836                 ]
 837             # b mantissa greater than a, use b
 838             with m.Else():
 839                 m.d.comb += [
 840                     self.o.tot.eq(bm0 - am0),
 841                     self.o.z.s.eq(self.i.b.s)
 842             ]
 843
 844         m.d.comb += self.o.oz.eq(self.i.oz)
 845         m.d.comb += self.o.out_do_z.eq(self.i.out_do_z)
 846         m.d.comb += self.o.mid.eq(self.i.mid)
 847         return m
 848
 849
 850 class FPAddStage0(FPState):
 851     """ First stage of add.  covers same-sign (add) and subtract
 852         special-casing when mantissas are greater or equal, to
 853         give greatest accuracy.
 854     """
 855
 856     def __init__(self, width, id_wid):
 857         FPState.__init__(self, "add_0")
 858         self.mod = FPAddStage0Mod(width)
 859         self.o = self.mod.ospec()
 860
 861     def setup(self, m, i):
 862         """ links module to inputs and outputs
 863         """
 864         self.mod.setup(m, i)
 865
 866         # NOTE: these could be done as combinatorial (merge add0+add1)
 867         m.d.sync += self.o.eq(self.mod.o)
 868
 869     def action(self, m):
 870         m.next = "add_1"
 871
 872
 873 class FPAddStage1Data:
 874
 875     def __init__(self, width, id_wid):
 876         self.z = FPNumBase(width, False)
 877         self.out_do_z = Signal(reset_less=True)
 878         self.oz = Signal(width, reset_less=True)
 879         self.of = Overflow()
 880         self.mid = Signal(id_wid, reset_less=True)
 881
 882     def eq(self, i):
 883         return [self.z.eq(i.z), self.out_do_z.eq(i.out_do_z), self.oz.eq(i.oz),
 884                 self.of.eq(i.of), self.mid.eq(i.mid)]
 885
 886
 887
 888 class FPAddStage1Mod(FPState):
 889     """ Second stage of add: preparation for normalisation.
 890         detects when tot sum is too big (tot[27] is kinda a carry bit)
 891     """
 892
 893     def __init__(self, width, id_wid):
 894         self.width = width
 895         self.id_wid = id_wid
 896         self.i = self.ispec()
 897         self.o = self.ospec()
 898
 899     def ispec(self):
 900         return FPAddStage0Data(self.width, self.id_wid)
 901
 902     def ospec(self):
 903         return FPAddStage1Data(self.width, self.id_wid)
 904
 905     def process(self, i):
 906         return self.o
 907
 908     def setup(self, m, i):
 909         """ links module to inputs and outputs
 910         """
 911         m.submodules.add1 = self
 912         m.submodules.add1_out_overflow = self.o.of
 913
 914         m.d.comb += self.i.eq(i)
 915
 916     def elaborate(self, platform):
 917         m = Module()
 918         #m.submodules.norm1_in_overflow = self.in_of
 919         #m.submodules.norm1_out_overflow = self.out_of
 920         #m.submodules.norm1_in_z = self.in_z
 921         #m.submodules.norm1_out_z = self.out_z
 922         m.d.comb += self.o.z.eq(self.i.z)
 923         # tot[-1] (MSB) gets set when the sum overflows. shift result down
 924         with m.If(~self.i.out_do_z):
 925             with m.If(self.i.tot[-1]):
 926                 m.d.comb += [
 927                     self.o.z.m.eq(self.i.tot[4:]),
 928                     self.o.of.m0.eq(self.i.tot[4]),
 929                     self.o.of.guard.eq(self.i.tot[3]),
 930                     self.o.of.round_bit.eq(self.i.tot[2]),
 931                     self.o.of.sticky.eq(self.i.tot[1] | self.i.tot[0]),
 932                     self.o.z.e.eq(self.i.z.e + 1)
 933             ]
 934             # tot[-1] (MSB) zero case
 935             with m.Else():
 936                 m.d.comb += [
 937                     self.o.z.m.eq(self.i.tot[3:]),
 938                     self.o.of.m0.eq(self.i.tot[3]),
 939                     self.o.of.guard.eq(self.i.tot[2]),
 940                     self.o.of.round_bit.eq(self.i.tot[1]),
 941                     self.o.of.sticky.eq(self.i.tot[0])
 942             ]
 943
 944         m.d.comb += self.o.out_do_z.eq(self.i.out_do_z)
 945         m.d.comb += self.o.oz.eq(self.i.oz)
 946         m.d.comb += self.o.mid.eq(self.i.mid)
 947
 948         return m
 949
 950
 951 class FPAddStage1(FPState):
 952
 953     def __init__(self, width, id_wid):
 954         FPState.__init__(self, "add_1")
 955         self.mod = FPAddStage1Mod(width)
 956         self.out_z = FPNumBase(width, False)
 957         self.out_of = Overflow()
 958         self.norm_stb = Signal()
 959
 960     def setup(self, m, i):
 961         """ links module to inputs and outputs
 962         """
 963         self.mod.setup(m, i)
 964
 965         m.d.sync += self.norm_stb.eq(0) # sets to zero when not in add1 state
 966
 967         m.d.sync += self.out_of.eq(self.mod.out_of)
 968         m.d.sync += self.out_z.eq(self.mod.out_z)
 969         m.d.sync += self.norm_stb.eq(1)
 970
 971     def action(self, m):
 972         m.next = "normalise_1"
 973
 974
 975 class FPNormaliseModSingle:
 976
 977     def __init__(self, width):
 978         self.width = width
 979         self.in_z = self.ispec()
 980         self.out_z = self.ospec()
 981
 982     def ispec(self):
 983         return FPNumBase(self.width, False)
 984
 985     def ospec(self):
 986         return FPNumBase(self.width, False)
 987
 988     def setup(self, m, i):
 989         """ links module to inputs and outputs
 990         """
 991         m.submodules.normalise = self
 992         m.d.comb += self.i.eq(i)
 993
 994     def elaborate(self, platform):
 995         m = Module()
 996
 997         mwid = self.out_z.m_width+2
 998         pe = PriorityEncoder(mwid)
 999         m.submodules.norm_pe = pe
1000
1001         m.submodules.norm1_out_z = self.out_z
1002         m.submodules.norm1_in_z = self.in_z
1003
1004         in_z = FPNumBase(self.width, False)
1005         in_of = Overflow()
1006         m.submodules.norm1_insel_z = in_z
1007         m.submodules.norm1_insel_overflow = in_of
1008
1009         espec = (len(in_z.e), True)
1010         ediff_n126 = Signal(espec, reset_less=True)
1011         msr = MultiShiftRMerge(mwid, espec)
1012         m.submodules.multishift_r = msr
1013
1014         m.d.comb += in_z.eq(self.in_z)
1015         m.d.comb += in_of.eq(self.in_of)
1016         # initialise out from in (overridden below)
1017         m.d.comb += self.out_z.eq(in_z)
1018         m.d.comb += self.out_of.eq(in_of)
1019         # normalisation decrease condition
1020         decrease = Signal(reset_less=True)
1021         m.d.comb += decrease.eq(in_z.m_msbzero)
1022         # decrease exponent
1023         with m.If(decrease):
1024             # *sigh* not entirely obvious: count leading zeros (clz)
1025             # with a PriorityEncoder: to find from the MSB
1026             # we reverse the order of the bits.
1027             temp_m = Signal(mwid, reset_less=True)
1028             temp_s = Signal(mwid+1, reset_less=True)
1029             clz = Signal((len(in_z.e), True), reset_less=True)
1030             m.d.comb += [
1031                 # cat round and guard bits back into the mantissa
1032                 temp_m.eq(Cat(in_of.round_bit, in_of.guard, in_z.m)),
1033                 pe.i.eq(temp_m[::-1]),          # inverted
1034                 clz.eq(pe.o),                   # count zeros from MSB down
1035                 temp_s.eq(temp_m << clz),       # shift mantissa UP
1036                 self.out_z.e.eq(in_z.e - clz),  # DECREASE exponent
1037                 self.out_z.m.eq(temp_s[2:]),    # exclude bits 0&1
1038             ]
1039
1040         return m
1041
1042 class FPNorm1Data:
1043
1044     def __init__(self, width, id_wid):
1045         self.roundz = Signal(reset_less=True)
1046         self.z = FPNumBase(width, False)
1047         self.out_do_z = Signal(reset_less=True)
1048         self.oz = Signal(width, reset_less=True)
1049         self.mid = Signal(id_wid, reset_less=True)
1050
1051     def eq(self, i):
1052         return [self.z.eq(i.z), self.out_do_z.eq(i.out_do_z), self.oz.eq(i.oz),
1053                 self.roundz.eq(i.roundz), self.mid.eq(i.mid)]
1054
1055
1056 class FPNorm1ModSingle:
1057
1058     def __init__(self, width, id_wid):
1059         self.width = width
1060         self.id_wid = id_wid
1061         self.i = self.ispec()
1062         self.o = self.ospec()
1063
1064     def ispec(self):
1065         return FPAddStage1Data(self.width, self.id_wid)
1066
1067     def ospec(self):
1068         return FPNorm1Data(self.width, self.id_wid)
1069
1070     def setup(self, m, i):
1071         """ links module to inputs and outputs
1072         """
1073         m.submodules.normalise_1 = self
1074         m.d.comb += self.i.eq(i)
1075
1076     def process(self, i):
1077         return self.o
1078
1079     def elaborate(self, platform):
1080         m = Module()
1081
1082         mwid = self.o.z.m_width+2
1083         pe = PriorityEncoder(mwid)
1084         m.submodules.norm_pe = pe
1085
1086         of = Overflow()
1087         m.d.comb += self.o.roundz.eq(of.roundz)
1088
1089         m.submodules.norm1_out_z = self.o.z
1090         m.submodules.norm1_out_overflow = of
1091         m.submodules.norm1_in_z = self.i.z
1092         m.submodules.norm1_in_overflow = self.i.of
1093
1094         i = self.ispec()
1095         m.submodules.norm1_insel_z = i.z
1096         m.submodules.norm1_insel_overflow = i.of
1097
1098         espec = (len(i.z.e), True)
1099         ediff_n126 = Signal(espec, reset_less=True)
1100         msr = MultiShiftRMerge(mwid, espec)
1101         m.submodules.multishift_r = msr
1102
1103         m.d.comb += i.eq(self.i)
1104         # initialise out from in (overridden below)
1105         m.d.comb += self.o.z.eq(i.z)
1106         m.d.comb += of.eq(i.of)
1107         # normalisation increase/decrease conditions
1108         decrease = Signal(reset_less=True)
1109         increase = Signal(reset_less=True)
1110         m.d.comb += decrease.eq(i.z.m_msbzero & i.z.exp_gt_n126)
1111         m.d.comb += increase.eq(i.z.exp_lt_n126)
1112         # decrease exponent
1113         with m.If(~self.i.out_do_z):
1114             with m.If(decrease):
1115                 # *sigh* not entirely obvious: count leading zeros (clz)
1116                 # with a PriorityEncoder: to find from the MSB
1117                 # we reverse the order of the bits.
1118                 temp_m = Signal(mwid, reset_less=True)
1119                 temp_s = Signal(mwid+1, reset_less=True)
1120                 clz = Signal((len(i.z.e), True), reset_less=True)
1121                 # make sure that the amount to decrease by does NOT
1122                 # go below the minimum non-INF/NaN exponent
1123                 limclz = Mux(i.z.exp_sub_n126 > pe.o, pe.o,
1124                              i.z.exp_sub_n126)
1125                 m.d.comb += [
1126                     # cat round and guard bits back into the mantissa
1127                     temp_m.eq(Cat(i.of.round_bit, i.of.guard, i.z.m)),
1128                     pe.i.eq(temp_m[::-1]),          # inverted
1129                     clz.eq(limclz),                 # count zeros from MSB down
1130                     temp_s.eq(temp_m << clz),       # shift mantissa UP
1131                     self.o.z.e.eq(i.z.e - clz),  # DECREASE exponent
1132                     self.o.z.m.eq(temp_s[2:]),    # exclude bits 0&1
1133                     of.m0.eq(temp_s[2]),          # copy of mantissa[0]
1134                     # overflow in bits 0..1: got shifted too (leave sticky)
1135                     of.guard.eq(temp_s[1]),       # guard
1136                     of.round_bit.eq(temp_s[0]),   # round
1137                 ]
1138             # increase exponent
1139             with m.Elif(increase):
1140                 temp_m = Signal(mwid+1, reset_less=True)
1141                 m.d.comb += [
1142                     temp_m.eq(Cat(i.of.sticky, i.of.round_bit, i.of.guard,
1143                                   i.z.m)),
1144                     ediff_n126.eq(i.z.N126 - i.z.e),
1145                     # connect multi-shifter to inp/out mantissa (and ediff)
1146                     msr.inp.eq(temp_m),
1147                     msr.diff.eq(ediff_n126),
1148                     self.o.z.m.eq(msr.m[3:]),
1149                     of.m0.eq(temp_s[3]),   # copy of mantissa[0]
1150                     # overflow in bits 0..1: got shifted too (leave sticky)
1151                     of.guard.eq(temp_s[2]),     # guard
1152                     of.round_bit.eq(temp_s[1]), # round
1153                     of.sticky.eq(temp_s[0]),    # sticky
1154                     self.o.z.e.eq(i.z.e + ediff_n126),
1155                 ]
1156
1157         m.d.comb += self.o.mid.eq(self.i.mid)
1158         m.d.comb += self.o.out_do_z.eq(self.i.out_do_z)
1159         m.d.comb += self.o.oz.eq(self.i.oz)
1160
1161         return m
1162
1163
1164 class FPNorm1ModMulti:
1165
1166     def __init__(self, width, single_cycle=True):
1167         self.width = width
1168         self.in_select = Signal(reset_less=True)
1169         self.in_z = FPNumBase(width, False)
1170         self.in_of = Overflow()
1171         self.temp_z = FPNumBase(width, False)
1172         self.temp_of = Overflow()
1173         self.out_z = FPNumBase(width, False)
1174         self.out_of = Overflow()
1175
1176     def elaborate(self, platform):
1177         m = Module()
1178
1179         m.submodules.norm1_out_z = self.out_z
1180         m.submodules.norm1_out_overflow = self.out_of
1181         m.submodules.norm1_temp_z = self.temp_z
1182         m.submodules.norm1_temp_of = self.temp_of
1183         m.submodules.norm1_in_z = self.in_z
1184         m.submodules.norm1_in_overflow = self.in_of
1185
1186         in_z = FPNumBase(self.width, False)
1187         in_of = Overflow()
1188         m.submodules.norm1_insel_z = in_z
1189         m.submodules.norm1_insel_overflow = in_of
1190
1191         # select which of temp or in z/of to use
1192         with m.If(self.in_select):
1193             m.d.comb += in_z.eq(self.in_z)
1194             m.d.comb += in_of.eq(self.in_of)
1195         with m.Else():
1196             m.d.comb += in_z.eq(self.temp_z)
1197             m.d.comb += in_of.eq(self.temp_of)
1198         # initialise out from in (overridden below)
1199         m.d.comb += self.out_z.eq(in_z)
1200         m.d.comb += self.out_of.eq(in_of)
1201         # normalisation increase/decrease conditions
1202         decrease = Signal(reset_less=True)
1203         increase = Signal(reset_less=True)
1204         m.d.comb += decrease.eq(in_z.m_msbzero & in_z.exp_gt_n126)
1205         m.d.comb += increase.eq(in_z.exp_lt_n126)
1206         m.d.comb += self.out_norm.eq(decrease | increase) # loop-end
1207         # decrease exponent
1208         with m.If(decrease):
1209             m.d.comb += [
1210                 self.out_z.e.eq(in_z.e - 1),  # DECREASE exponent
1211                 self.out_z.m.eq(in_z.m << 1), # shift mantissa UP
1212                 self.out_z.m[0].eq(in_of.guard), # steal guard (was tot[2])
1213                 self.out_of.guard.eq(in_of.round_bit), # round (was tot[1])
1214                 self.out_of.round_bit.eq(0),        # reset round bit
1215                 self.out_of.m0.eq(in_of.guard),
1216             ]
1217         # increase exponent
1218         with m.Elif(increase):
1219             m.d.comb += [
1220                 self.out_z.e.eq(in_z.e + 1),  # INCREASE exponent
1221                 self.out_z.m.eq(in_z.m >> 1), # shift mantissa DOWN
1222                 self.out_of.guard.eq(in_z.m[0]),
1223                 self.out_of.m0.eq(in_z.m[1]),
1224                 self.out_of.round_bit.eq(in_of.guard),
1225                 self.out_of.sticky.eq(in_of.sticky | in_of.round_bit)
1226             ]
1227
1228         return m
1229
1230
1231 class FPNorm1Single(FPState):
1232
1233     def __init__(self, width, id_wid, single_cycle=True):
1234         FPState.__init__(self, "normalise_1")
1235         self.mod = FPNorm1ModSingle(width)
1236         self.o = self.ospec()
1237         self.out_z = FPNumBase(width, False)
1238         self.out_roundz = Signal(reset_less=True)
1239
1240     def ispec(self):
1241         return self.mod.ispec()
1242
1243     def ospec(self):
1244         return self.mod.ospec()
1245
1246     def setup(self, m, i):
1247         """ links module to inputs and outputs
1248         """
1249         self.mod.setup(m, i)
1250
1251     def action(self, m):
1252         m.next = "round"
1253
1254
1255 class FPNorm1Multi(FPState):
1256
1257     def __init__(self, width, id_wid):
1258         FPState.__init__(self, "normalise_1")
1259         self.mod = FPNorm1ModMulti(width)
1260         self.stb = Signal(reset_less=True)
1261         self.ack = Signal(reset=0, reset_less=True)
1262         self.out_norm = Signal(reset_less=True)
1263         self.in_accept = Signal(reset_less=True)
1264         self.temp_z = FPNumBase(width)
1265         self.temp_of = Overflow()
1266         self.out_z = FPNumBase(width)
1267         self.out_roundz = Signal(reset_less=True)
1268
1269     def setup(self, m, in_z, in_of, norm_stb):
1270         """ links module to inputs and outputs
1271         """
1272         self.mod.setup(m, in_z, in_of, norm_stb,
1273                        self.in_accept, self.temp_z, self.temp_of,
1274                        self.out_z, self.out_norm)
1275
1276         m.d.comb += self.stb.eq(norm_stb)
1277         m.d.sync += self.ack.eq(0) # sets to zero when not in normalise_1 state
1278
1279     def action(self, m):
1280         m.d.comb += self.in_accept.eq((~self.ack) & (self.stb))
1281         m.d.sync += self.temp_of.eq(self.mod.out_of)
1282         m.d.sync += self.temp_z.eq(self.out_z)
1283         with m.If(self.out_norm):
1284             with m.If(self.in_accept):
1285                 m.d.sync += [
1286                     self.ack.eq(1),
1287                 ]
1288             with m.Else():
1289                 m.d.sync += self.ack.eq(0)
1290         with m.Else():
1291             # normalisation not required (or done).
1292             m.next = "round"
1293             m.d.sync += self.ack.eq(1)
1294             m.d.sync += self.out_roundz.eq(self.mod.out_of.roundz)
1295
1296
1297 class FPNormToPack(FPState):
1298
1299     def __init__(self, width, id_wid):
1300         FPState.__init__(self, "normalise_1")
1301         self.id_wid = id_wid
1302         self.width = width
1303
1304     def ispec(self):
1305         return FPAddStage1Data(self.width, self.id_wid) # Norm1ModSingle ispec
1306
1307     def ospec(self):
1308         return FPPackData(self.width, self.id_wid) # FPPackMod ospec
1309
1310     def setup(self, m, i):
1311         """ links module to inputs and outputs
1312         """
1313
1314         # Normalisation, Rounding Corrections, Pack - in a chain
1315         nmod = FPNorm1ModSingle(self.width, self.id_wid)
1316         rmod = FPRoundMod(self.width, self.id_wid)
1317         cmod = FPCorrectionsMod(self.width, self.id_wid)
1318         pmod = FPPackMod(self.width, self.id_wid)
1319         chain = StageChain([nmod, rmod, cmod, pmod])
1320         chain.setup(m, i)
1321         self.out_z = pmod.ospec()
1322
1323         m.d.sync += self.out_z.mid.eq(pmod.o.mid)
1324         m.d.sync += self.out_z.z.v.eq(pmod.o.z.v) # outputs packed result
1325
1326     def action(self, m):
1327         m.next = "pack_put_z"
1328
1329
1330 class FPRoundData:
1331
1332     def __init__(self, width, id_wid):
1333         self.z = FPNumBase(width, False)
1334         self.out_do_z = Signal(reset_less=True)
1335         self.oz = Signal(width, reset_less=True)
1336         self.mid = Signal(id_wid, reset_less=True)
1337
1338     def eq(self, i):
1339         return [self.z.eq(i.z), self.out_do_z.eq(i.out_do_z), self.oz.eq(i.oz),
1340                 self.mid.eq(i.mid)]
1341
1342
1343 class FPRoundMod:
1344
1345     def __init__(self, width, id_wid):
1346         self.width = width
1347         self.id_wid = id_wid
1348         self.i = self.ispec()
1349         self.out_z = self.ospec()
1350
1351     def ispec(self):
1352         return FPNorm1Data(self.width, self.id_wid)
1353
1354     def ospec(self):
1355         return FPRoundData(self.width, self.id_wid)
1356
1357     def process(self, i):
1358         return self.out_z
1359
1360     def setup(self, m, i):
1361         m.submodules.roundz = self
1362         m.d.comb += self.i.eq(i)
1363
1364     def elaborate(self, platform):
1365         m = Module()
1366         m.d.comb += self.out_z.eq(self.i) # copies mid, z, out_do_z
1367         with m.If(~self.i.out_do_z):
1368             with m.If(self.i.roundz):
1369                 m.d.comb += self.out_z.z.m.eq(self.i.z.m + 1) # mantissa up
1370                 with m.If(self.i.z.m == self.i.z.m1s): # all 1s
1371                     m.d.comb += self.out_z.z.e.eq(self.i.z.e + 1) # exponent up
1372
1373         return m
1374
1375
1376 class FPRound(FPState):
1377
1378     def __init__(self, width, id_wid):
1379         FPState.__init__(self, "round")
1380         self.mod = FPRoundMod(width)
1381         self.out_z = self.ospec()
1382
1383     def ispec(self):
1384         return self.mod.ispec()
1385
1386     def ospec(self):
1387         return self.mod.ospec()
1388
1389     def setup(self, m, i):
1390         """ links module to inputs and outputs
1391         """
1392         self.mod.setup(m, i)
1393
1394         self.idsync(m)
1395         m.d.sync += self.out_z.eq(self.mod.out_z)
1396         m.d.sync += self.out_z.mid.eq(self.mod.o.mid)
1397
1398     def action(self, m):
1399         m.next = "corrections"
1400
1401
1402 class FPCorrectionsMod:
1403
1404     def __init__(self, width, id_wid):
1405         self.width = width
1406         self.id_wid = id_wid
1407         self.i = self.ispec()
1408         self.out_z = self.ospec()
1409
1410     def ispec(self):
1411         return FPRoundData(self.width, self.id_wid)
1412
1413     def ospec(self):
1414         return FPRoundData(self.width, self.id_wid)
1415
1416     def process(self, i):
1417         return self.out_z
1418
1419     def setup(self, m, i):
1420         """ links module to inputs and outputs
1421         """
1422         m.submodules.corrections = self
1423         m.d.comb += self.i.eq(i)
1424
1425     def elaborate(self, platform):
1426         m = Module()
1427         m.submodules.corr_in_z = self.i.z
1428         m.submodules.corr_out_z = self.out_z.z
1429         m.d.comb += self.out_z.eq(self.i) # copies mid, z, out_do_z
1430         with m.If(~self.i.out_do_z):
1431             with m.If(self.i.z.is_denormalised):
1432                 m.d.comb += self.out_z.z.e.eq(self.i.z.N127)
1433         return m
1434
1435
1436 class FPCorrections(FPState):
1437
1438     def __init__(self, width, id_wid):
1439         FPState.__init__(self, "corrections")
1440         self.mod = FPCorrectionsMod(width)
1441         self.out_z = self.ospec()
1442
1443     def ispec(self):
1444         return self.mod.ispec()
1445
1446     def ospec(self):
1447         return self.mod.ospec()
1448
1449     def setup(self, m, in_z):
1450         """ links module to inputs and outputs
1451         """
1452         self.mod.setup(m, in_z)
1453
1454         m.d.sync += self.out_z.eq(self.mod.out_z)
1455         m.d.sync += self.out_z.mid.eq(self.mod.o.mid)
1456
1457     def action(self, m):
1458         m.next = "pack"
1459
1460
1461 class FPPackData:
1462
1463     def __init__(self, width, id_wid):
1464         self.z = FPNumOut(width, False)
1465         self.mid = Signal(id_wid, reset_less=True)
1466
1467     def eq(self, i):
1468         return [self.z.eq(i.z), self.mid.eq(i.mid)]
1469
1470
1471 class FPPackMod:
1472
1473     def __init__(self, width, id_wid):
1474         self.width = width
1475         self.id_wid = id_wid
1476         self.i = self.ispec()
1477         self.o = self.ospec()
1478
1479     def ispec(self):
1480         return FPRoundData(self.width, self.id_wid)
1481
1482     def ospec(self):
1483         return FPPackData(self.width, self.id_wid)
1484
1485     def process(self, i):
1486         return self.o
1487
1488     def setup(self, m, in_z):
1489         """ links module to inputs and outputs
1490         """
1491         m.submodules.pack = self
1492         m.d.comb += self.i.eq(in_z)
1493
1494     def elaborate(self, platform):
1495         m = Module()
1496         m.submodules.pack_in_z = self.i.z
1497         m.d.comb += self.o.mid.eq(self.i.mid)
1498         with m.If(~self.i.out_do_z):
1499             with m.If(self.i.z.is_overflowed):
1500                 m.d.comb += self.o.z.inf(self.i.z.s)
1501             with m.Else():
1502                 m.d.comb += self.o.z.create(self.i.z.s, self.i.z.e, self.i.z.m)
1503         with m.Else():
1504             m.d.comb += self.o.z.v.eq(self.i.oz)
1505         return m
1506
1507
1508 class FPPack(FPState):
1509
1510     def __init__(self, width, id_wid):
1511         FPState.__init__(self, "pack")
1512         self.mod = FPPackMod(width)
1513         self.out_z = self.ospec()
1514
1515     def ispec(self):
1516         return self.mod.ispec()
1517
1518     def ospec(self):
1519         return self.mod.ospec()
1520
1521     def setup(self, m, in_z):
1522         """ links module to inputs and outputs
1523         """
1524         self.mod.setup(m, in_z)
1525
1526         m.d.sync += self.out_z.v.eq(self.mod.out_z.v)
1527         m.d.sync += self.out_z.mid.eq(self.mod.o.mid)
1528
1529     def action(self, m):
1530         m.next = "pack_put_z"
1531
1532
1533 class FPPutZ(FPState):
1534
1535     def __init__(self, state, in_z, out_z, in_mid, out_mid, to_state=None):
1536         FPState.__init__(self, state)
1537         if to_state is None:
1538             to_state = "get_ops"
1539         self.to_state = to_state
1540         self.in_z = in_z
1541         self.out_z = out_z
1542         self.in_mid = in_mid
1543         self.out_mid = out_mid
1544
1545     def action(self, m):
1546         if self.in_mid is not None:
1547             m.d.sync += self.out_mid.eq(self.in_mid)
1548         m.d.sync += [
1549           self.out_z.z.v.eq(self.in_z.v)
1550         ]
1551         with m.If(self.out_z.z.stb & self.out_z.z.ack):
1552             m.d.sync += self.out_z.z.stb.eq(0)
1553             m.next = self.to_state
1554         with m.Else():
1555             m.d.sync += self.out_z.z.stb.eq(1)
1556
1557
1558 class FPPutZIdx(FPState):
1559
1560     def __init__(self, state, in_z, out_zs, in_mid, to_state=None):
1561         FPState.__init__(self, state)
1562         if to_state is None:
1563             to_state = "get_ops"
1564         self.to_state = to_state
1565         self.in_z = in_z
1566         self.out_zs = out_zs
1567         self.in_mid = in_mid
1568
1569     def action(self, m):
1570         outz_stb = Signal(reset_less=True)
1571         outz_ack = Signal(reset_less=True)
1572         m.d.comb += [outz_stb.eq(self.out_zs[self.in_mid].stb),
1573                      outz_ack.eq(self.out_zs[self.in_mid].ack),
1574                     ]
1575         m.d.sync += [
1576           self.out_zs[self.in_mid].v.eq(self.in_z.v)
1577         ]
1578         with m.If(outz_stb & outz_ack):
1579             m.d.sync += self.out_zs[self.in_mid].stb.eq(0)
1580             m.next = self.to_state
1581         with m.Else():
1582             m.d.sync += self.out_zs[self.in_mid].stb.eq(1)
1583
1584 class FPADDBaseData:
1585
1586     def __init__(self, width, id_wid):
1587         self.width = width
1588         self.id_wid = id_wid
1589         self.a  = Signal(width)
1590         self.b  = Signal(width)
1591         self.mid = Signal(id_wid, reset_less=True)
1592
1593     def eq(self, i):
1594         return [self.a.eq(i.a), self.b.eq(i.b), self.mid.eq(i.mid)]
1595
1596
1597 class FPOpData:
1598     def __init__(self, width, id_wid):
1599         self.z = FPOp(width)
1600         self.mid = Signal(id_wid, reset_less=True)
1601
1602     def eq(self, i):
1603         return [self.z.eq(i.z), self.mid.eq(i.mid)]
1604
1605
1606 class FPADDBaseMod:
1607
1608     def __init__(self, width, id_wid=None, single_cycle=False, compact=True):
1609         """ IEEE754 FP Add
1610
1611             * width: bit-width of IEEE754.  supported: 16, 32, 64
1612             * id_wid: an identifier that is sync-connected to the input
1613             * single_cycle: True indicates each stage to complete in 1 clock
1614             * compact: True indicates a reduced number of stages
1615         """
1616         self.width = width
1617         self.id_wid = id_wid
1618         self.single_cycle = single_cycle
1619         self.compact = compact
1620
1621         self.in_t = Trigger()
1622         self.i = self.ispec()
1623         self.o = self.ospec()
1624
1625         self.states = []
1626
1627     def ispec(self):
1628         return FPADDBaseData(self.width, self.id_wid)
1629
1630     def ospec(self):
1631         return FPOpData(self.width, self.id_wid)
1632
1633     def add_state(self, state):
1634         self.states.append(state)
1635         return state
1636
1637     def get_fragment(self, platform=None):
1638         """ creates the HDL code-fragment for FPAdd
1639         """
1640         m = Module()
1641         m.submodules.out_z = self.o.z
1642         m.submodules.in_t = self.in_t
1643         if self.compact:
1644             self.get_compact_fragment(m, platform)
1645         else:
1646             self.get_longer_fragment(m, platform)
1647
1648         with m.FSM() as fsm:
1649
1650             for state in self.states:
1651                 with m.State(state.state_from):
1652                     state.action(m)
1653
1654         return m
1655
1656     def get_longer_fragment(self, m, platform=None):
1657
1658         get = self.add_state(FPGet2Op("get_ops", "special_cases",
1659                                       self.width))
1660         get.setup(m, self.i, self.in_t.stb, self.in_t.ack)
1661         a = get.out_op1
1662         b = get.out_op2
1663
1664         sc = self.add_state(FPAddSpecialCases(self.width, self.id_wid))
1665         sc.setup(m, a, b, self.in_mid)
1666
1667         dn = self.add_state(FPAddDeNorm(self.width, self.id_wid))
1668         dn.setup(m, a, b, sc.in_mid)
1669
1670         if self.single_cycle:
1671             alm = self.add_state(FPAddAlignSingle(self.width, self.id_wid))
1672             alm.setup(m, dn.out_a, dn.out_b, dn.in_mid)
1673         else:
1674             alm = self.add_state(FPAddAlignMulti(self.width, self.id_wid))
1675             alm.setup(m, dn.out_a, dn.out_b, dn.in_mid)
1676
1677         add0 = self.add_state(FPAddStage0(self.width, self.id_wid))
1678         add0.setup(m, alm.out_a, alm.out_b, alm.in_mid)
1679
1680         add1 = self.add_state(FPAddStage1(self.width, self.id_wid))
1681         add1.setup(m, add0.out_tot, add0.out_z, add0.in_mid)
1682
1683         if self.single_cycle:
1684             n1 = self.add_state(FPNorm1Single(self.width, self.id_wid))
1685             n1.setup(m, add1.out_z, add1.out_of, add0.in_mid)
1686         else:
1687             n1 = self.add_state(FPNorm1Multi(self.width, self.id_wid))
1688             n1.setup(m, add1.out_z, add1.out_of, add1.norm_stb, add0.in_mid)
1689
1690         rn = self.add_state(FPRound(self.width, self.id_wid))
1691         rn.setup(m, n1.out_z, n1.out_roundz, n1.in_mid)
1692
1693         cor = self.add_state(FPCorrections(self.width, self.id_wid))
1694         cor.setup(m, rn.out_z, rn.in_mid)
1695
1696         pa = self.add_state(FPPack(self.width, self.id_wid))
1697         pa.setup(m, cor.out_z, rn.in_mid)
1698
1699         ppz = self.add_state(FPPutZ("pack_put_z", pa.out_z, self.out_z,
1700                                     pa.in_mid, self.out_mid))
1701
1702         pz = self.add_state(FPPutZ("put_z", sc.out_z, self.out_z,
1703                                     pa.in_mid, self.out_mid))
1704
1705     def get_compact_fragment(self, m, platform=None):
1706
1707         get = self.add_state(FPGet2Op("get_ops", "special_cases",
1708                                       self.width, self.id_wid))
1709         get.setup(m, self.i, self.in_t.stb, self.in_t.ack)
1710
1711         sc = self.add_state(FPAddSpecialCasesDeNorm(self.width, self.id_wid))
1712         sc.setup(m, get.o)
1713
1714         alm = self.add_state(FPAddAlignSingleAdd(self.width, self.id_wid))
1715         alm.setup(m, sc.o)
1716
1717         n1 = self.add_state(FPNormToPack(self.width, self.id_wid))
1718         n1.setup(m, alm.a1o)
1719
1720         ppz = self.add_state(FPPutZ("pack_put_z", n1.out_z.z, self.o,
1721                                     n1.out_z.mid, self.o.mid))
1722
1723         #pz = self.add_state(FPPutZ("put_z", sc.out_z.z, self.o,
1724         #                            sc.o.mid, self.o.mid))
1725
1726
1727 class FPADDBase(FPState):
1728
1729     def __init__(self, width, id_wid=None, single_cycle=False):
1730         """ IEEE754 FP Add
1731
1732             * width: bit-width of IEEE754.  supported: 16, 32, 64
1733             * id_wid: an identifier that is sync-connected to the input
1734             * single_cycle: True indicates each stage to complete in 1 clock
1735         """
1736         FPState.__init__(self, "fpadd")
1737         self.width = width
1738         self.single_cycle = single_cycle
1739         self.mod = FPADDBaseMod(width, id_wid, single_cycle)
1740         self.o = self.ospec()
1741
1742         self.in_t = Trigger()
1743         self.i = self.ispec()
1744
1745         self.z_done = Signal(reset_less=True) # connects to out_z Strobe
1746         self.in_accept = Signal(reset_less=True)
1747         self.add_stb = Signal(reset_less=True)
1748         self.add_ack = Signal(reset=0, reset_less=True)
1749
1750     def ispec(self):
1751         return self.mod.ispec()
1752
1753     def ospec(self):
1754         return self.mod.ospec()
1755
1756     def setup(self, m, i, add_stb, in_mid):
1757         m.d.comb += [self.i.eq(i),
1758                      self.mod.i.eq(self.i),
1759                      self.z_done.eq(self.mod.o.z.trigger),
1760                      #self.add_stb.eq(add_stb),
1761                      self.mod.in_t.stb.eq(self.in_t.stb),
1762                      self.in_t.ack.eq(self.mod.in_t.ack),
1763                      self.o.mid.eq(self.mod.o.mid),
1764                      self.o.z.v.eq(self.mod.o.z.v),
1765                      self.o.z.stb.eq(self.mod.o.z.stb),
1766                      self.mod.o.z.ack.eq(self.o.z.ack),
1767                     ]
1768
1769         m.d.sync += self.add_stb.eq(add_stb)
1770         m.d.sync += self.add_ack.eq(0) # sets to zero when not in active state
1771         m.d.sync += self.o.z.ack.eq(0) # likewise
1772         #m.d.sync += self.in_t.stb.eq(0)
1773
1774         m.submodules.fpadd = self.mod
1775
1776     def action(self, m):
1777
1778         # in_accept is set on incoming strobe HIGH and ack LOW.
1779         m.d.comb += self.in_accept.eq((~self.add_ack) & (self.add_stb))
1780
1781         #with m.If(self.in_t.ack):
1782         #    m.d.sync += self.in_t.stb.eq(0)
1783         with m.If(~self.z_done):
1784             # not done: test for accepting an incoming operand pair
1785             with m.If(self.in_accept):
1786                 m.d.sync += [
1787                     self.add_ack.eq(1), # acknowledge receipt...
1788                     self.in_t.stb.eq(1), # initiate add
1789                 ]
1790             with m.Else():
1791                 m.d.sync += [self.add_ack.eq(0),
1792                              self.in_t.stb.eq(0),
1793                              self.o.z.ack.eq(1),
1794                             ]
1795         with m.Else():
1796             # done: acknowledge, and write out id and value
1797             m.d.sync += [self.add_ack.eq(1),
1798                          self.in_t.stb.eq(0)
1799                         ]
1800             m.next = "put_z"
1801
1802             return
1803
1804             if self.in_mid is not None:
1805                 m.d.sync += self.out_mid.eq(self.mod.out_mid)
1806
1807             m.d.sync += [
1808               self.out_z.v.eq(self.mod.out_z.v)
1809             ]
1810             # move to output state on detecting z ack
1811             with m.If(self.out_z.trigger):
1812                 m.d.sync += self.out_z.stb.eq(0)
1813                 m.next = "put_z"
1814             with m.Else():
1815                 m.d.sync += self.out_z.stb.eq(1)
1816
1817 class FPADDStageIn:
1818     def __init__(self, width, id_wid):
1819         self.a = Signal(width)
1820         self.b = Signal(width)
1821         self.mid = Signal(id_wid, reset_less=True)
1822
1823     def eq(self, i):
1824         return [self.a.eq(i.a), self.b.eq(i.b), self.mid.eq(i.mid)]
1825
1826
1827 class FPADDStageOut:
1828     def __init__(self, width, id_wid):
1829         self.z = Signal(width)
1830         self.mid = Signal(id_wid, reset_less=True)
1831
1832     def eq(self, i):
1833         return [self.z.eq(i.z), self.mid.eq(i.mid)]
1834
1835
1836 # matches the format of FPADDStageOut, allows eq function to do assignments
1837 class PlaceHolder: pass
1838
1839
1840 class FPAddBaseStage:
1841     def __init__(self, width, id_wid):
1842         self.width = width
1843         self.id_wid = id_wid
1844
1845     def ispec(self):
1846         return FPADDStageIn(self.width, self.id_wid)
1847
1848     def ospec(self):
1849         return FPADDStageOut(self.width, self.id_wid)
1850
1851     def process(self, i):
1852         o = PlaceHolder()
1853         o.z = i.a + i.b
1854         o.mid = i.mid
1855         return o
1856
1857
1858 class FPADDBasePipe:
1859     def __init__(self, width, id_wid):
1860         stage1 = FPAddBaseStage(width, id_wid)
1861         self.pipe = UnbufferedPipeline(stage1)
1862
1863     def elaborate(self, platform):
1864         return self.pipe.elaborate(platform)
1865
1866     def ports(self):
1867         return self.pipe.ports()
1868
1869 class ResArray:
1870     def __init__(self, width, id_wid):
1871         self.width = width
1872         self.id_wid = id_wid
1873         res = []
1874         for i in range(rs_sz):
1875             out_z = FPOp(width)
1876             out_z.name = "out_z_%d" % i
1877             res.append(out_z)
1878         self.res = Array(res)
1879         self.in_z = FPOp(width)
1880         self.in_mid = Signal(self.id_wid, reset_less=True)
1881
1882     def setup(self, m, in_z, in_mid):
1883         m.d.comb += [self.in_z.eq(in_z),
1884                      self.in_mid.eq(in_mid)]
1885
1886     def get_fragment(self, platform=None):
1887         """ creates the HDL code-fragment for FPAdd
1888         """
1889         m = Module()
1890         m.submodules.res_in_z = self.in_z
1891         m.submodules += self.res
1892
1893         return m
1894
1895     def ports(self):
1896         res = []
1897         for z in self.res:
1898             res += z.ports()
1899         return res
1900
1901
1902 class FPADD(FPID):
1903     """ FPADD: stages as follows:
1904
1905         FPGetOp (a)
1906            |
1907         FPGetOp (b)
1908            |
1909         FPAddBase---> FPAddBaseMod
1910            |            |
1911         PutZ          GetOps->Specials->Align->Add1/2->Norm->Round/Pack->PutZ
1912
1913         FPAddBase is tricky: it is both a stage and *has* stages.
1914         Connection to FPAddBaseMod therefore requires an in stb/ack
1915         and an out stb/ack.  Just as with Add1-Norm1 interaction, FPGetOp
1916         needs to be the thing that raises the incoming stb.
1917     """
1918
1919     def __init__(self, width, id_wid=None, single_cycle=False, rs_sz=2):
1920         """ IEEE754 FP Add
1921
1922             * width: bit-width of IEEE754.  supported: 16, 32, 64
1923             * id_wid: an identifier that is sync-connected to the input
1924             * single_cycle: True indicates each stage to complete in 1 clock
1925         """
1926         self.width = width
1927         self.id_wid = id_wid
1928         self.single_cycle = single_cycle
1929
1930         #self.out_z = FPOp(width)
1931         self.ids = FPID(id_wid)
1932
1933         rs = []
1934         for i in range(rs_sz):
1935             in_a  = FPOp(width)
1936             in_b  = FPOp(width)
1937             in_a.name = "in_a_%d" % i
1938             in_b.name = "in_b_%d" % i
1939             rs.append((in_a, in_b))
1940         self.rs = Array(rs)
1941
1942         res = []
1943         for i in range(rs_sz):
1944             out_z = FPOp(width)
1945             out_z.name = "out_z_%d" % i
1946             res.append(out_z)
1947         self.res = Array(res)
1948
1949         self.states = []
1950
1951     def add_state(self, state):
1952         self.states.append(state)
1953         return state
1954
1955     def get_fragment(self, platform=None):
1956         """ creates the HDL code-fragment for FPAdd
1957         """
1958         m = Module()
1959         m.submodules += self.rs
1960
1961         in_a = self.rs[0][0]
1962         in_b = self.rs[0][1]
1963
1964         geta = self.add_state(FPGetOp("get_a", "get_b",
1965                                       in_a, self.width))
1966         geta.setup(m, in_a)
1967         a = geta.out_op
1968
1969         getb = self.add_state(FPGetOp("get_b", "fpadd",
1970                                       in_b, self.width))
1971         getb.setup(m, in_b)
1972         b = getb.out_op
1973
1974         ab = FPADDBase(self.width, self.id_wid, self.single_cycle)
1975         ab = self.add_state(ab)
1976         abd = ab.ispec() # create an input spec object for FPADDBase
1977         m.d.sync += [abd.a.eq(a), abd.b.eq(b), abd.mid.eq(self.ids.in_mid)]
1978         ab.setup(m, abd, getb.out_decode, self.ids.in_mid)
1979         o = ab.o
1980
1981         pz = self.add_state(FPPutZIdx("put_z", o.z, self.res,
1982                                     o.mid, "get_a"))
1983
1984         with m.FSM() as fsm:
1985
1986             for state in self.states:
1987                 with m.State(state.state_from):
1988                     state.action(m)
1989
1990         return m
1991
1992
1993 if __name__ == "__main__":
1994     if True:
1995         alu = FPADD(width=32, id_wid=5, single_cycle=True)
1996         main(alu, ports=alu.rs[0][0].ports() + \
1997                         alu.rs[0][1].ports() + \
1998                         alu.res[0].ports() + \
1999                         [alu.ids.in_mid, alu.ids.out_mid])
2000     else:
2001         alu = FPADDBase(width=32, id_wid=5, single_cycle=True)
2002         main(alu, ports=[alu.in_a, alu.in_b] + \
2003                         alu.in_t.ports() + \
2004                         alu.out_z.ports() + \
2005                         [alu.in_mid, alu.out_mid])
2006
2007
2008     # works... but don't use, just do "python fname.py convert -t v"
2009     #print (verilog.convert(alu, ports=[
2010     #                        ports=alu.in_a.ports() + \
2011     #                              alu.in_b.ports() + \
2012     #                              alu.out_z.ports())