src/add/nmigen_add_experiment.py

   1 # IEEE Floating Point Adder (Single Precision)
   2 # Copyright (C) Jonathan P Dawson 2013
   3 # 2013-12-12
   4
   5 from nmigen import Module, Signal, Cat, Mux, Array, Const
   6 from nmigen.lib.coding import PriorityEncoder
   7 from nmigen.cli import main, verilog
   8 from math import log
   9
  10 from fpbase import FPNumIn, FPNumOut, FPOp, Overflow, FPBase, FPNumBase
  11 from fpbase import MultiShiftRMerge, Trigger
  12 from example_buf_pipe import StageChain
  13 #from fpbase import FPNumShiftMultiRight
  14
  15
  16 class FPState(FPBase):
  17     def __init__(self, state_from):
  18         self.state_from = state_from
  19
  20     def set_inputs(self, inputs):
  21         self.inputs = inputs
  22         for k,v in inputs.items():
  23             setattr(self, k, v)
  24
  25     def set_outputs(self, outputs):
  26         self.outputs = outputs
  27         for k,v in outputs.items():
  28             setattr(self, k, v)
  29
  30
  31 class FPGetSyncOpsMod:
  32     def __init__(self, width, num_ops=2):
  33         self.width = width
  34         self.num_ops = num_ops
  35         inops = []
  36         outops = []
  37         for i in range(num_ops):
  38             inops.append(Signal(width, reset_less=True))
  39             outops.append(Signal(width, reset_less=True))
  40         self.in_op = inops
  41         self.out_op = outops
  42         self.stb = Signal(num_ops)
  43         self.ack = Signal()
  44         self.ready = Signal(reset_less=True)
  45         self.out_decode = Signal(reset_less=True)
  46
  47     def elaborate(self, platform):
  48         m = Module()
  49         m.d.comb += self.ready.eq(self.stb == Const(-1, (self.num_ops, False)))
  50         m.d.comb += self.out_decode.eq(self.ack & self.ready)
  51         with m.If(self.out_decode):
  52             for i in range(self.num_ops):
  53                 m.d.comb += [
  54                         self.out_op[i].eq(self.in_op[i]),
  55                 ]
  56         return m
  57
  58     def ports(self):
  59         return self.in_op + self.out_op + [self.stb, self.ack]
  60
  61
  62 class FPOps(Trigger):
  63     def __init__(self, width, num_ops):
  64         Trigger.__init__(self)
  65         self.width = width
  66         self.num_ops = num_ops
  67
  68         res = []
  69         for i in range(num_ops):
  70             res.append(Signal(width))
  71         self.v  = Array(res)
  72
  73     def ports(self):
  74         res = []
  75         for i in range(self.num_ops):
  76             res.append(self.v[i])
  77         res.append(self.ack)
  78         res.append(self.stb)
  79         return res
  80
  81
  82 class InputGroup:
  83     def __init__(self, width, num_ops=2, num_rows=4):
  84         self.width = width
  85         self.num_ops = num_ops
  86         self.num_rows = num_rows
  87         self.mmax = int(log(self.num_rows) / log(2))
  88         self.rs = []
  89         self.mid = Signal(self.mmax, reset_less=True) # multiplex id
  90         for i in range(num_rows):
  91             self.rs.append(FPGetSyncOpsMod(width, num_ops))
  92         self.rs = Array(self.rs)
  93
  94         self.out_op = FPOps(width, num_ops)
  95
  96     def elaborate(self, platform):
  97         m = Module()
  98
  99         pe = PriorityEncoder(self.num_rows)
 100         m.submodules.selector = pe
 101         m.submodules.out_op = self.out_op
 102         m.submodules += self.rs
 103
 104         # connect priority encoder
 105         in_ready = []
 106         for i in range(self.num_rows):
 107             in_ready.append(self.rs[i].ready)
 108         m.d.comb += pe.i.eq(Cat(*in_ready))
 109
 110         active = Signal(reset_less=True)
 111         out_en = Signal(reset_less=True)
 112         m.d.comb += active.eq(~pe.n) # encoder active
 113         m.d.comb += out_en.eq(active & self.out_op.trigger)
 114
 115         # encoder active: ack relevant input, record MID, pass output
 116         with m.If(out_en):
 117             rs = self.rs[pe.o]
 118             m.d.sync += self.mid.eq(pe.o)
 119             m.d.sync += rs.ack.eq(0)
 120             m.d.sync += self.out_op.stb.eq(0)
 121             for j in range(self.num_ops):
 122                 m.d.sync += self.out_op.v[j].eq(rs.out_op[j])
 123         with m.Else():
 124             m.d.sync += self.out_op.stb.eq(1)
 125             # acks all default to zero
 126             for i in range(self.num_rows):
 127                 m.d.sync += self.rs[i].ack.eq(1)
 128
 129         return m
 130
 131     def ports(self):
 132         res = []
 133         for i in range(self.num_rows):
 134             inop = self.rs[i]
 135             res += inop.in_op + [inop.stb]
 136         return self.out_op.ports() + res + [self.mid]
 137
 138
 139 class FPGetOpMod:
 140     def __init__(self, width):
 141         self.in_op = FPOp(width)
 142         self.out_op = Signal(width)
 143         self.out_decode = Signal(reset_less=True)
 144
 145     def elaborate(self, platform):
 146         m = Module()
 147         m.d.comb += self.out_decode.eq((self.in_op.ack) & (self.in_op.stb))
 148         m.submodules.get_op_in = self.in_op
 149         #m.submodules.get_op_out = self.out_op
 150         with m.If(self.out_decode):
 151             m.d.comb += [
 152                 self.out_op.eq(self.in_op.v),
 153             ]
 154         return m
 155
 156
 157 class FPGetOp(FPState):
 158     """ gets operand
 159     """
 160
 161     def __init__(self, in_state, out_state, in_op, width):
 162         FPState.__init__(self, in_state)
 163         self.out_state = out_state
 164         self.mod = FPGetOpMod(width)
 165         self.in_op = in_op
 166         self.out_op = Signal(width)
 167         self.out_decode = Signal(reset_less=True)
 168
 169     def setup(self, m, in_op):
 170         """ links module to inputs and outputs
 171         """
 172         setattr(m.submodules, self.state_from, self.mod)
 173         m.d.comb += self.mod.in_op.eq(in_op)
 174         m.d.comb += self.out_decode.eq(self.mod.out_decode)
 175
 176     def action(self, m):
 177         with m.If(self.out_decode):
 178             m.next = self.out_state
 179             m.d.sync += [
 180                 self.in_op.ack.eq(0),
 181                 self.out_op.eq(self.mod.out_op)
 182             ]
 183         with m.Else():
 184             m.d.sync += self.in_op.ack.eq(1)
 185
 186
 187 class FPGet2OpMod(Trigger):
 188     def __init__(self, width, id_wid):
 189         Trigger.__init__(self)
 190         self.width = width
 191         self.id_wid = id_wid
 192         self.i = self.ispec()
 193         self.o = self.ospec()
 194
 195     def ispec(self):
 196         return FPADDBaseData(self.width, self.id_wid)
 197
 198     def ospec(self):
 199         return FPNumBase2Ops(self.width, self.id_wid)
 200
 201     def elaborate(self, platform):
 202         m = Trigger.elaborate(self, platform)
 203         m.submodules.get_op1_out = self.o.a
 204         m.submodules.get_op2_out = self.o.b
 205         out_op1 = FPNumIn(None, self.width)
 206         out_op2 = FPNumIn(None, self.width)
 207         with m.If(self.trigger):
 208             m.d.comb += [
 209                 out_op1.decode(self.i.a),
 210                 out_op2.decode(self.i.b),
 211                 self.o.a.eq(out_op1),
 212                 self.o.b.eq(out_op2),
 213                 self.o.mid.eq(self.i.mid)
 214             ]
 215         return m
 216
 217
 218 class FPGet2Op(FPState):
 219     """ gets operands
 220     """
 221
 222     def __init__(self, in_state, out_state, width, id_wid):
 223         FPState.__init__(self, in_state)
 224         self.out_state = out_state
 225         self.mod = FPGet2OpMod(width, id_wid)
 226         self.o = self.mod.ospec()
 227         self.in_stb = Signal(reset_less=True)
 228         self.out_ack = Signal(reset_less=True)
 229         self.out_decode = Signal(reset_less=True)
 230
 231     def setup(self, m, i, in_stb, in_ack):
 232         """ links module to inputs and outputs
 233         """
 234         m.submodules.get_ops = self.mod
 235         m.d.comb += self.mod.i.eq(i)
 236         m.d.comb += self.mod.stb.eq(in_stb)
 237         m.d.comb += self.out_ack.eq(self.mod.ack)
 238         m.d.comb += self.out_decode.eq(self.mod.trigger)
 239         m.d.comb += in_ack.eq(self.mod.ack)
 240
 241     def action(self, m):
 242         with m.If(self.out_decode):
 243             m.next = self.out_state
 244             m.d.sync += [
 245                 self.mod.ack.eq(0),
 246                 self.o.eq(self.mod.o),
 247             ]
 248         with m.Else():
 249             m.d.sync += self.mod.ack.eq(1)
 250
 251
 252 class FPNumBase2Ops:
 253
 254     def __init__(self, width, id_wid, m_extra=True):
 255         self.a = FPNumBase(width, m_extra)
 256         self.b = FPNumBase(width, m_extra)
 257         self.mid = Signal(id_wid, reset_less=True)
 258
 259     def eq(self, i):
 260         return [self.a.eq(i.a), self.b.eq(i.b), self.mid.eq(i.mid)]
 261
 262
 263 class FPSCData:
 264
 265     def __init__(self, width, id_wid):
 266         self.a = FPNumBase(width, True)
 267         self.b = FPNumBase(width, True)
 268         self.z = FPNumOut(width, False)
 269         self.oz = Signal(width, reset_less=True)
 270         self.out_do_z = Signal(reset_less=True)
 271         self.mid = Signal(id_wid, reset_less=True)
 272
 273     def eq(self, i):
 274         return [self.z.eq(i.z), self.out_do_z.eq(i.out_do_z), self.oz.eq(i.oz),
 275                 self.a.eq(i.a), self.b.eq(i.b), self.mid.eq(i.mid)]
 276
 277
 278 class FPAddSpecialCasesMod:
 279     """ special cases: NaNs, infs, zeros, denormalised
 280         NOTE: some of these are unique to add.  see "Special Operations"
 281         https://steve.hollasch.net/cgindex/coding/ieeefloat.html
 282     """
 283
 284     def __init__(self, width, id_wid):
 285         self.width = width
 286         self.id_wid = id_wid
 287         self.i = self.ispec()
 288         self.o = self.ospec()
 289
 290     def ispec(self):
 291         return FPNumBase2Ops(self.width, self.id_wid)
 292
 293     def ospec(self):
 294         return FPSCData(self.width, self.id_wid)
 295
 296     def setup(self, m, i):
 297         """ links module to inputs and outputs
 298         """
 299         m.submodules.specialcases = self
 300         m.d.comb += self.i.eq(i)
 301
 302     def elaborate(self, platform):
 303         m = Module()
 304
 305         m.submodules.sc_in_a = self.i.a
 306         m.submodules.sc_in_b = self.i.b
 307         m.submodules.sc_out_z = self.o.z
 308
 309         s_nomatch = Signal()
 310         m.d.comb += s_nomatch.eq(self.i.a.s != self.i.b.s)
 311
 312         m_match = Signal()
 313         m.d.comb += m_match.eq(self.i.a.m == self.i.b.m)
 314
 315         # if a is NaN or b is NaN return NaN
 316         with m.If(self.i.a.is_nan | self.i.b.is_nan):
 317             m.d.comb += self.o.out_do_z.eq(1)
 318             m.d.comb += self.o.z.nan(0)
 319
 320         # XXX WEIRDNESS for FP16 non-canonical NaN handling
 321         # under review
 322
 323         ## if a is zero and b is NaN return -b
 324         #with m.If(a.is_zero & (a.s==0) & b.is_nan):
 325         #    m.d.comb += self.o.out_do_z.eq(1)
 326         #    m.d.comb += z.create(b.s, b.e, Cat(b.m[3:-2], ~b.m[0]))
 327
 328         ## if b is zero and a is NaN return -a
 329         #with m.Elif(b.is_zero & (b.s==0) & a.is_nan):
 330         #    m.d.comb += self.o.out_do_z.eq(1)
 331         #    m.d.comb += z.create(a.s, a.e, Cat(a.m[3:-2], ~a.m[0]))
 332
 333         ## if a is -zero and b is NaN return -b
 334         #with m.Elif(a.is_zero & (a.s==1) & b.is_nan):
 335         #    m.d.comb += self.o.out_do_z.eq(1)
 336         #    m.d.comb += z.create(a.s & b.s, b.e, Cat(b.m[3:-2], 1))
 337
 338         ## if b is -zero and a is NaN return -a
 339         #with m.Elif(b.is_zero & (b.s==1) & a.is_nan):
 340         #    m.d.comb += self.o.out_do_z.eq(1)
 341         #    m.d.comb += z.create(a.s & b.s, a.e, Cat(a.m[3:-2], 1))
 342
 343         # if a is inf return inf (or NaN)
 344         with m.Elif(self.i.a.is_inf):
 345             m.d.comb += self.o.out_do_z.eq(1)
 346             m.d.comb += self.o.z.inf(self.i.a.s)
 347             # if a is inf and signs don't match return NaN
 348             with m.If(self.i.b.exp_128 & s_nomatch):
 349                 m.d.comb += self.o.z.nan(0)
 350
 351         # if b is inf return inf
 352         with m.Elif(self.i.b.is_inf):
 353             m.d.comb += self.o.out_do_z.eq(1)
 354             m.d.comb += self.o.z.inf(self.i.b.s)
 355
 356         # if a is zero and b zero return signed-a/b
 357         with m.Elif(self.i.a.is_zero & self.i.b.is_zero):
 358             m.d.comb += self.o.out_do_z.eq(1)
 359             m.d.comb += self.o.z.create(self.i.a.s & self.i.b.s,
 360                                           self.i.b.e,
 361                                           self.i.b.m[3:-1])
 362
 363         # if a is zero return b
 364         with m.Elif(self.i.a.is_zero):
 365             m.d.comb += self.o.out_do_z.eq(1)
 366             m.d.comb += self.o.z.create(self.i.b.s, self.i.b.e,
 367                                       self.i.b.m[3:-1])
 368
 369         # if b is zero return a
 370         with m.Elif(self.i.b.is_zero):
 371             m.d.comb += self.o.out_do_z.eq(1)
 372             m.d.comb += self.o.z.create(self.i.a.s, self.i.a.e,
 373                                       self.i.a.m[3:-1])
 374
 375         # if a equal to -b return zero (+ve zero)
 376         with m.Elif(s_nomatch & m_match & (self.i.a.e == self.i.b.e)):
 377             m.d.comb += self.o.out_do_z.eq(1)
 378             m.d.comb += self.o.z.zero(0)
 379
 380         # Denormalised Number checks next, so pass a/b data through
 381         with m.Else():
 382             m.d.comb += self.o.out_do_z.eq(0)
 383             m.d.comb += self.o.a.eq(self.i.a)
 384             m.d.comb += self.o.b.eq(self.i.b)
 385
 386         m.d.comb += self.o.oz.eq(self.o.z.v)
 387         m.d.comb += self.o.mid.eq(self.i.mid)
 388
 389         return m
 390
 391
 392 class FPID:
 393     def __init__(self, id_wid):
 394         self.id_wid = id_wid
 395         if self.id_wid:
 396             self.in_mid = Signal(id_wid, reset_less=True)
 397             self.out_mid = Signal(id_wid, reset_less=True)
 398         else:
 399             self.in_mid = None
 400             self.out_mid = None
 401
 402     def idsync(self, m):
 403         if self.id_wid is not None:
 404             m.d.sync += self.out_mid.eq(self.in_mid)
 405
 406
 407 class FPAddSpecialCases(FPState):
 408     """ special cases: NaNs, infs, zeros, denormalised
 409         NOTE: some of these are unique to add.  see "Special Operations"
 410         https://steve.hollasch.net/cgindex/coding/ieeefloat.html
 411     """
 412
 413     def __init__(self, width, id_wid):
 414         FPState.__init__(self, "special_cases")
 415         self.mod = FPAddSpecialCasesMod(width)
 416         self.out_z = self.mod.ospec()
 417         self.out_do_z = Signal(reset_less=True)
 418
 419     def setup(self, m, i):
 420         """ links module to inputs and outputs
 421         """
 422         self.mod.setup(m, i, self.out_do_z)
 423         m.d.sync += self.out_z.v.eq(self.mod.out_z.v) # only take the output
 424         m.d.sync += self.out_z.mid.eq(self.mod.o.mid)  # (and mid)
 425
 426     def action(self, m):
 427         self.idsync(m)
 428         with m.If(self.out_do_z):
 429             m.next = "put_z"
 430         with m.Else():
 431             m.next = "denormalise"
 432
 433
 434 class FPAddSpecialCasesDeNorm(FPState):
 435     """ special cases: NaNs, infs, zeros, denormalised
 436         NOTE: some of these are unique to add.  see "Special Operations"
 437         https://steve.hollasch.net/cgindex/coding/ieeefloat.html
 438     """
 439
 440     def __init__(self, width, id_wid):
 441         FPState.__init__(self, "special_cases")
 442         self.smod = FPAddSpecialCasesMod(width, id_wid)
 443         self.out_z = self.smod.ospec()
 444         self.out_do_z = Signal(reset_less=True)
 445
 446         self.dmod = FPAddDeNormMod(width, id_wid)
 447         self.o = self.dmod.ospec()
 448
 449     def setup(self, m, i):
 450         """ links module to inputs and outputs
 451         """
 452         self.smod.setup(m, i)
 453         self.dmod.setup(m, self.smod.o)
 454         m.d.comb += self.out_do_z.eq(self.smod.o.out_do_z)
 455
 456         # out_do_z=True
 457         m.d.sync += self.out_z.z.v.eq(self.smod.o.z.v) # only take output
 458         m.d.sync += self.out_z.mid.eq(self.smod.o.mid)  # (and mid)
 459         # out_do_z=False
 460         m.d.sync += self.o.eq(self.dmod.o)
 461
 462     def action(self, m):
 463         with m.If(self.out_do_z):
 464             m.next = "put_z"
 465         with m.Else():
 466             m.next = "align"
 467
 468
 469 class FPAddDeNormMod(FPState):
 470
 471     def __init__(self, width, id_wid):
 472         self.width = width
 473         self.id_wid = id_wid
 474         self.i = self.ispec()
 475         self.o = self.ospec()
 476
 477     def ispec(self):
 478         return FPSCData(self.width, self.id_wid)
 479
 480     def ospec(self):
 481         return FPSCData(self.width, self.id_wid)
 482
 483     def setup(self, m, i):
 484         """ links module to inputs and outputs
 485         """
 486         m.submodules.denormalise = self
 487         m.d.comb += self.i.eq(i)
 488
 489     def elaborate(self, platform):
 490         m = Module()
 491         m.submodules.denorm_in_a = self.i.a
 492         m.submodules.denorm_in_b = self.i.b
 493         m.submodules.denorm_out_a = self.o.a
 494         m.submodules.denorm_out_b = self.o.b
 495
 496         with m.If(~self.i.out_do_z):
 497             # XXX hmmm, don't like repeating identical code
 498             m.d.comb += self.o.a.eq(self.i.a)
 499             with m.If(self.i.a.exp_n127):
 500                 m.d.comb += self.o.a.e.eq(self.i.a.N126) # limit a exponent
 501             with m.Else():
 502                 m.d.comb += self.o.a.m[-1].eq(1) # set top mantissa bit
 503
 504             m.d.comb += self.o.b.eq(self.i.b)
 505             with m.If(self.i.b.exp_n127):
 506                 m.d.comb += self.o.b.e.eq(self.i.b.N126) # limit a exponent
 507             with m.Else():
 508                 m.d.comb += self.o.b.m[-1].eq(1) # set top mantissa bit
 509
 510         m.d.comb += self.o.mid.eq(self.i.mid)
 511         m.d.comb += self.o.z.eq(self.i.z)
 512         m.d.comb += self.o.out_do_z.eq(self.i.out_do_z)
 513         m.d.comb += self.o.oz.eq(self.i.oz)
 514
 515         return m
 516
 517
 518 class FPAddDeNorm(FPState):
 519
 520     def __init__(self, width, id_wid):
 521         FPState.__init__(self, "denormalise")
 522         self.mod = FPAddDeNormMod(width)
 523         self.out_a = FPNumBase(width)
 524         self.out_b = FPNumBase(width)
 525
 526     def setup(self, m, i):
 527         """ links module to inputs and outputs
 528         """
 529         self.mod.setup(m, i)
 530
 531         m.d.sync += self.out_a.eq(self.mod.out_a)
 532         m.d.sync += self.out_b.eq(self.mod.out_b)
 533
 534     def action(self, m):
 535         # Denormalised Number checks
 536         m.next = "align"
 537
 538
 539 class FPAddAlignMultiMod(FPState):
 540
 541     def __init__(self, width):
 542         self.in_a = FPNumBase(width)
 543         self.in_b = FPNumBase(width)
 544         self.out_a = FPNumIn(None, width)
 545         self.out_b = FPNumIn(None, width)
 546         self.exp_eq = Signal(reset_less=True)
 547
 548     def elaborate(self, platform):
 549         # This one however (single-cycle) will do the shift
 550         # in one go.
 551
 552         m = Module()
 553
 554         m.submodules.align_in_a = self.in_a
 555         m.submodules.align_in_b = self.in_b
 556         m.submodules.align_out_a = self.out_a
 557         m.submodules.align_out_b = self.out_b
 558
 559         # NOTE: this does *not* do single-cycle multi-shifting,
 560         #       it *STAYS* in the align state until exponents match
 561
 562         # exponent of a greater than b: shift b down
 563         m.d.comb += self.exp_eq.eq(0)
 564         m.d.comb += self.out_a.eq(self.in_a)
 565         m.d.comb += self.out_b.eq(self.in_b)
 566         agtb = Signal(reset_less=True)
 567         altb = Signal(reset_less=True)
 568         m.d.comb += agtb.eq(self.in_a.e > self.in_b.e)
 569         m.d.comb += altb.eq(self.in_a.e < self.in_b.e)
 570         with m.If(agtb):
 571             m.d.comb += self.out_b.shift_down(self.in_b)
 572         # exponent of b greater than a: shift a down
 573         with m.Elif(altb):
 574             m.d.comb += self.out_a.shift_down(self.in_a)
 575         # exponents equal: move to next stage.
 576         with m.Else():
 577             m.d.comb += self.exp_eq.eq(1)
 578         return m
 579
 580
 581 class FPAddAlignMulti(FPState):
 582
 583     def __init__(self, width, id_wid):
 584         FPState.__init__(self, "align")
 585         self.mod = FPAddAlignMultiMod(width)
 586         self.out_a = FPNumIn(None, width)
 587         self.out_b = FPNumIn(None, width)
 588         self.exp_eq = Signal(reset_less=True)
 589
 590     def setup(self, m, in_a, in_b):
 591         """ links module to inputs and outputs
 592         """
 593         m.submodules.align = self.mod
 594         m.d.comb += self.mod.in_a.eq(in_a)
 595         m.d.comb += self.mod.in_b.eq(in_b)
 596         #m.d.comb += self.out_a.eq(self.mod.out_a)
 597         #m.d.comb += self.out_b.eq(self.mod.out_b)
 598         m.d.comb += self.exp_eq.eq(self.mod.exp_eq)
 599         m.d.sync += self.out_a.eq(self.mod.out_a)
 600         m.d.sync += self.out_b.eq(self.mod.out_b)
 601
 602     def action(self, m):
 603         with m.If(self.exp_eq):
 604             m.next = "add_0"
 605
 606
 607 class FPNumIn2Ops:
 608
 609     def __init__(self, width, id_wid):
 610         self.a = FPNumIn(None, width)
 611         self.b = FPNumIn(None, width)
 612         self.z = FPNumOut(width, False)
 613         self.out_do_z = Signal(reset_less=True)
 614         self.oz = Signal(width, reset_less=True)
 615         self.mid = Signal(id_wid, reset_less=True)
 616
 617     def eq(self, i):
 618         return [self.z.eq(i.z), self.out_do_z.eq(i.out_do_z), self.oz.eq(i.oz),
 619                 self.a.eq(i.a), self.b.eq(i.b), self.mid.eq(i.mid)]
 620
 621
 622 class FPAddAlignSingleMod:
 623
 624     def __init__(self, width, id_wid):
 625         self.width = width
 626         self.id_wid = id_wid
 627         self.i = self.ispec()
 628         self.o = self.ospec()
 629
 630     def ispec(self):
 631         return FPSCData(self.width, self.id_wid)
 632
 633     def ospec(self):
 634         return FPNumIn2Ops(self.width, self.id_wid)
 635
 636     def process(self, i):
 637         return self.o
 638
 639     def setup(self, m, i):
 640         """ links module to inputs and outputs
 641         """
 642         m.submodules.align = self
 643         m.d.comb += self.i.eq(i)
 644
 645     def elaborate(self, platform):
 646         """ Aligns A against B or B against A, depending on which has the
 647             greater exponent.  This is done in a *single* cycle using
 648             variable-width bit-shift
 649
 650             the shifter used here is quite expensive in terms of gates.
 651             Mux A or B in (and out) into temporaries, as only one of them
 652             needs to be aligned against the other
 653         """
 654         m = Module()
 655
 656         m.submodules.align_in_a = self.i.a
 657         m.submodules.align_in_b = self.i.b
 658         m.submodules.align_out_a = self.o.a
 659         m.submodules.align_out_b = self.o.b
 660
 661         # temporary (muxed) input and output to be shifted
 662         t_inp = FPNumBase(self.width)
 663         t_out = FPNumIn(None, self.width)
 664         espec = (len(self.i.a.e), True)
 665         msr = MultiShiftRMerge(self.i.a.m_width, espec)
 666         m.submodules.align_t_in = t_inp
 667         m.submodules.align_t_out = t_out
 668         m.submodules.multishift_r = msr
 669
 670         ediff = Signal(espec, reset_less=True)
 671         ediffr = Signal(espec, reset_less=True)
 672         tdiff = Signal(espec, reset_less=True)
 673         elz = Signal(reset_less=True)
 674         egz = Signal(reset_less=True)
 675
 676         # connect multi-shifter to t_inp/out mantissa (and tdiff)
 677         m.d.comb += msr.inp.eq(t_inp.m)
 678         m.d.comb += msr.diff.eq(tdiff)
 679         m.d.comb += t_out.m.eq(msr.m)
 680         m.d.comb += t_out.e.eq(t_inp.e + tdiff)
 681         m.d.comb += t_out.s.eq(t_inp.s)
 682
 683         m.d.comb += ediff.eq(self.i.a.e - self.i.b.e)
 684         m.d.comb += ediffr.eq(self.i.b.e - self.i.a.e)
 685         m.d.comb += elz.eq(self.i.a.e < self.i.b.e)
 686         m.d.comb += egz.eq(self.i.a.e > self.i.b.e)
 687
 688         # default: A-exp == B-exp, A and B untouched (fall through)
 689         m.d.comb += self.o.a.eq(self.i.a)
 690         m.d.comb += self.o.b.eq(self.i.b)
 691         # only one shifter (muxed)
 692         #m.d.comb += t_out.shift_down_multi(tdiff, t_inp)
 693         # exponent of a greater than b: shift b down
 694         with m.If(~self.i.out_do_z):
 695             with m.If(egz):
 696                 m.d.comb += [t_inp.eq(self.i.b),
 697                              tdiff.eq(ediff),
 698                              self.o.b.eq(t_out),
 699                              self.o.b.s.eq(self.i.b.s), # whoops forgot sign
 700                             ]
 701             # exponent of b greater than a: shift a down
 702             with m.Elif(elz):
 703                 m.d.comb += [t_inp.eq(self.i.a),
 704                              tdiff.eq(ediffr),
 705                              self.o.a.eq(t_out),
 706                              self.o.a.s.eq(self.i.a.s), # whoops forgot sign
 707                             ]
 708
 709         m.d.comb += self.o.mid.eq(self.i.mid)
 710         m.d.comb += self.o.z.eq(self.i.z)
 711         m.d.comb += self.o.out_do_z.eq(self.i.out_do_z)
 712         m.d.comb += self.o.oz.eq(self.i.oz)
 713
 714         return m
 715
 716
 717 class FPAddAlignSingle(FPState):
 718
 719     def __init__(self, width, id_wid):
 720         FPState.__init__(self, "align")
 721         self.mod = FPAddAlignSingleMod(width, id_wid)
 722         self.out_a = FPNumIn(None, width)
 723         self.out_b = FPNumIn(None, width)
 724
 725     def setup(self, m, i):
 726         """ links module to inputs and outputs
 727         """
 728         self.mod.setup(m, i)
 729
 730         # NOTE: could be done as comb
 731         m.d.sync += self.out_a.eq(self.mod.out_a)
 732         m.d.sync += self.out_b.eq(self.mod.out_b)
 733
 734     def action(self, m):
 735         m.next = "add_0"
 736
 737
 738 class FPAddAlignSingleAdd(FPState):
 739
 740     def __init__(self, width, id_wid):
 741         FPState.__init__(self, "align")
 742         self.width = width
 743         self.id_wid = id_wid
 744         self.a1o = self.ospec()
 745
 746     def ispec(self):
 747         return FPNumBase2Ops(self.width, self.id_wid) # AlignSingle ispec
 748
 749     def ospec(self):
 750         return FPAddStage1Data(self.width, self.id_wid) # AddStage1 ospec
 751
 752     def setup(self, m, i):
 753         """ links module to inputs and outputs
 754         """
 755
 756         # chain AddAlignSingle, AddStage0 and AddStage1
 757         mod = FPAddAlignSingleMod(self.width, self.id_wid)
 758         a0mod = FPAddStage0Mod(self.width, self.id_wid)
 759         a1mod = FPAddStage1Mod(self.width, self.id_wid)
 760
 761         chain = StageChain([mod, a0mod, a1mod])
 762         chain.setup(m, i)
 763
 764         m.d.sync += self.a1o.eq(a1mod.o)
 765
 766     def action(self, m):
 767         m.next = "normalise_1"
 768
 769
 770 class FPAddStage0Data:
 771
 772     def __init__(self, width, id_wid):
 773         self.z = FPNumBase(width, False)
 774         self.out_do_z = Signal(reset_less=True)
 775         self.oz = Signal(width, reset_less=True)
 776         self.tot = Signal(self.z.m_width + 4, reset_less=True)
 777         self.mid = Signal(id_wid, reset_less=True)
 778
 779     def eq(self, i):
 780         return [self.z.eq(i.z), self.out_do_z.eq(i.out_do_z), self.oz.eq(i.oz),
 781                 self.tot.eq(i.tot), self.mid.eq(i.mid)]
 782
 783
 784 class FPAddStage0Mod:
 785
 786     def __init__(self, width, id_wid):
 787         self.width = width
 788         self.id_wid = id_wid
 789         self.i = self.ispec()
 790         self.o = self.ospec()
 791
 792     def ispec(self):
 793         return FPSCData(self.width, self.id_wid)
 794
 795     def ospec(self):
 796         return FPAddStage0Data(self.width, self.id_wid)
 797
 798     def process(self, i):
 799         return self.o
 800
 801     def setup(self, m, i):
 802         """ links module to inputs and outputs
 803         """
 804         m.submodules.add0 = self
 805         m.d.comb += self.i.eq(i)
 806
 807     def elaborate(self, platform):
 808         m = Module()
 809         m.submodules.add0_in_a = self.i.a
 810         m.submodules.add0_in_b = self.i.b
 811         m.submodules.add0_out_z = self.o.z
 812
 813         # store intermediate tests (and zero-extended mantissas)
 814         seq = Signal(reset_less=True)
 815         mge = Signal(reset_less=True)
 816         am0 = Signal(len(self.i.a.m)+1, reset_less=True)
 817         bm0 = Signal(len(self.i.b.m)+1, reset_less=True)
 818         m.d.comb += [seq.eq(self.i.a.s == self.i.b.s),
 819                      mge.eq(self.i.a.m >= self.i.b.m),
 820                      am0.eq(Cat(self.i.a.m, 0)),
 821                      bm0.eq(Cat(self.i.b.m, 0))
 822                     ]
 823         # same-sign (both negative or both positive) add mantissas
 824         with m.If(~self.i.out_do_z):
 825             m.d.comb += self.o.z.e.eq(self.i.a.e)
 826             with m.If(seq):
 827                 m.d.comb += [
 828                     self.o.tot.eq(am0 + bm0),
 829                     self.o.z.s.eq(self.i.a.s)
 830                 ]
 831             # a mantissa greater than b, use a
 832             with m.Elif(mge):
 833                 m.d.comb += [
 834                     self.o.tot.eq(am0 - bm0),
 835                     self.o.z.s.eq(self.i.a.s)
 836                 ]
 837             # b mantissa greater than a, use b
 838             with m.Else():
 839                 m.d.comb += [
 840                     self.o.tot.eq(bm0 - am0),
 841                     self.o.z.s.eq(self.i.b.s)
 842             ]
 843         with m.Else():
 844             m.d.comb += self.o.oz.eq(self.i.z.v)
 845
 846         m.d.comb += self.o.out_do_z.eq(self.i.out_do_z)
 847         m.d.comb += self.o.mid.eq(self.i.mid)
 848         return m
 849
 850
 851 class FPAddStage0(FPState):
 852     """ First stage of add.  covers same-sign (add) and subtract
 853         special-casing when mantissas are greater or equal, to
 854         give greatest accuracy.
 855     """
 856
 857     def __init__(self, width, id_wid):
 858         FPState.__init__(self, "add_0")
 859         self.mod = FPAddStage0Mod(width)
 860         self.o = self.mod.ospec()
 861
 862     def setup(self, m, i):
 863         """ links module to inputs and outputs
 864         """
 865         self.mod.setup(m, i)
 866
 867         # NOTE: these could be done as combinatorial (merge add0+add1)
 868         m.d.sync += self.o.eq(self.mod.o)
 869
 870     def action(self, m):
 871         m.next = "add_1"
 872
 873
 874 class FPAddStage1Data:
 875
 876     def __init__(self, width, id_wid):
 877         self.z = FPNumBase(width, False)
 878         self.out_do_z = Signal(reset_less=True)
 879         self.oz = Signal(width, reset_less=True)
 880         self.of = Overflow()
 881         self.mid = Signal(id_wid, reset_less=True)
 882
 883     def eq(self, i):
 884         return [self.z.eq(i.z), self.out_do_z.eq(i.out_do_z), self.oz.eq(i.oz),
 885                 self.of.eq(i.of), self.mid.eq(i.mid)]
 886
 887
 888
 889 class FPAddStage1Mod(FPState):
 890     """ Second stage of add: preparation for normalisation.
 891         detects when tot sum is too big (tot[27] is kinda a carry bit)
 892     """
 893
 894     def __init__(self, width, id_wid):
 895         self.width = width
 896         self.id_wid = id_wid
 897         self.i = self.ispec()
 898         self.o = self.ospec()
 899
 900     def ispec(self):
 901         return FPAddStage0Data(self.width, self.id_wid)
 902
 903     def ospec(self):
 904         return FPAddStage1Data(self.width, self.id_wid)
 905
 906     def process(self, i):
 907         return self.o
 908
 909     def setup(self, m, i):
 910         """ links module to inputs and outputs
 911         """
 912         m.submodules.add1 = self
 913         m.submodules.add1_out_overflow = self.o.of
 914
 915         m.d.comb += self.i.eq(i)
 916
 917     def elaborate(self, platform):
 918         m = Module()
 919         #m.submodules.norm1_in_overflow = self.in_of
 920         #m.submodules.norm1_out_overflow = self.out_of
 921         #m.submodules.norm1_in_z = self.in_z
 922         #m.submodules.norm1_out_z = self.out_z
 923         m.d.comb += self.o.z.eq(self.i.z)
 924         # tot[-1] (MSB) gets set when the sum overflows. shift result down
 925         with m.If(~self.i.out_do_z):
 926             with m.If(self.i.tot[-1]):
 927                 m.d.comb += [
 928                     self.o.z.m.eq(self.i.tot[4:]),
 929                     self.o.of.m0.eq(self.i.tot[4]),
 930                     self.o.of.guard.eq(self.i.tot[3]),
 931                     self.o.of.round_bit.eq(self.i.tot[2]),
 932                     self.o.of.sticky.eq(self.i.tot[1] | self.i.tot[0]),
 933                     self.o.z.e.eq(self.i.z.e + 1)
 934             ]
 935             # tot[-1] (MSB) zero case
 936             with m.Else():
 937                 m.d.comb += [
 938                     self.o.z.m.eq(self.i.tot[3:]),
 939                     self.o.of.m0.eq(self.i.tot[3]),
 940                     self.o.of.guard.eq(self.i.tot[2]),
 941                     self.o.of.round_bit.eq(self.i.tot[1]),
 942                     self.o.of.sticky.eq(self.i.tot[0])
 943             ]
 944
 945         m.d.comb += self.o.out_do_z.eq(self.i.out_do_z)
 946         m.d.comb += self.o.oz.eq(self.i.oz)
 947         m.d.comb += self.o.mid.eq(self.i.mid)
 948
 949         return m
 950
 951
 952 class FPAddStage1(FPState):
 953
 954     def __init__(self, width, id_wid):
 955         FPState.__init__(self, "add_1")
 956         self.mod = FPAddStage1Mod(width)
 957         self.out_z = FPNumBase(width, False)
 958         self.out_of = Overflow()
 959         self.norm_stb = Signal()
 960
 961     def setup(self, m, i):
 962         """ links module to inputs and outputs
 963         """
 964         self.mod.setup(m, i)
 965
 966         m.d.sync += self.norm_stb.eq(0) # sets to zero when not in add1 state
 967
 968         m.d.sync += self.out_of.eq(self.mod.out_of)
 969         m.d.sync += self.out_z.eq(self.mod.out_z)
 970         m.d.sync += self.norm_stb.eq(1)
 971
 972     def action(self, m):
 973         m.next = "normalise_1"
 974
 975
 976 class FPNormaliseModSingle:
 977
 978     def __init__(self, width):
 979         self.width = width
 980         self.in_z = self.ispec()
 981         self.out_z = self.ospec()
 982
 983     def ispec(self):
 984         return FPNumBase(self.width, False)
 985
 986     def ospec(self):
 987         return FPNumBase(self.width, False)
 988
 989     def setup(self, m, i):
 990         """ links module to inputs and outputs
 991         """
 992         m.submodules.normalise = self
 993         m.d.comb += self.i.eq(i)
 994
 995     def elaborate(self, platform):
 996         m = Module()
 997
 998         mwid = self.out_z.m_width+2
 999         pe = PriorityEncoder(mwid)
1000         m.submodules.norm_pe = pe
1001
1002         m.submodules.norm1_out_z = self.out_z
1003         m.submodules.norm1_in_z = self.in_z
1004
1005         in_z = FPNumBase(self.width, False)
1006         in_of = Overflow()
1007         m.submodules.norm1_insel_z = in_z
1008         m.submodules.norm1_insel_overflow = in_of
1009
1010         espec = (len(in_z.e), True)
1011         ediff_n126 = Signal(espec, reset_less=True)
1012         msr = MultiShiftRMerge(mwid, espec)
1013         m.submodules.multishift_r = msr
1014
1015         m.d.comb += in_z.eq(self.in_z)
1016         m.d.comb += in_of.eq(self.in_of)
1017         # initialise out from in (overridden below)
1018         m.d.comb += self.out_z.eq(in_z)
1019         m.d.comb += self.out_of.eq(in_of)
1020         # normalisation decrease condition
1021         decrease = Signal(reset_less=True)
1022         m.d.comb += decrease.eq(in_z.m_msbzero)
1023         # decrease exponent
1024         with m.If(decrease):
1025             # *sigh* not entirely obvious: count leading zeros (clz)
1026             # with a PriorityEncoder: to find from the MSB
1027             # we reverse the order of the bits.
1028             temp_m = Signal(mwid, reset_less=True)
1029             temp_s = Signal(mwid+1, reset_less=True)
1030             clz = Signal((len(in_z.e), True), reset_less=True)
1031             m.d.comb += [
1032                 # cat round and guard bits back into the mantissa
1033                 temp_m.eq(Cat(in_of.round_bit, in_of.guard, in_z.m)),
1034                 pe.i.eq(temp_m[::-1]),          # inverted
1035                 clz.eq(pe.o),                   # count zeros from MSB down
1036                 temp_s.eq(temp_m << clz),       # shift mantissa UP
1037                 self.out_z.e.eq(in_z.e - clz),  # DECREASE exponent
1038                 self.out_z.m.eq(temp_s[2:]),    # exclude bits 0&1
1039             ]
1040
1041         return m
1042
1043 class FPNorm1Data:
1044
1045     def __init__(self, width, id_wid):
1046         self.roundz = Signal(reset_less=True)
1047         self.z = FPNumBase(width, False)
1048         self.out_do_z = Signal(reset_less=True)
1049         self.oz = Signal(width, reset_less=True)
1050         self.mid = Signal(id_wid, reset_less=True)
1051
1052     def eq(self, i):
1053         return [self.z.eq(i.z), self.out_do_z.eq(i.out_do_z), self.oz.eq(i.oz),
1054                 self.roundz.eq(i.roundz), self.mid.eq(i.mid)]
1055
1056
1057 class FPNorm1ModSingle:
1058
1059     def __init__(self, width, id_wid):
1060         self.width = width
1061         self.id_wid = id_wid
1062         self.i = self.ispec()
1063         self.o = self.ospec()
1064
1065     def ispec(self):
1066         return FPAddStage1Data(self.width, self.id_wid)
1067
1068     def ospec(self):
1069         return FPNorm1Data(self.width, self.id_wid)
1070
1071     def setup(self, m, i):
1072         """ links module to inputs and outputs
1073         """
1074         m.submodules.normalise_1 = self
1075         m.d.comb += self.i.eq(i)
1076
1077     def process(self, i):
1078         return self.o
1079
1080     def elaborate(self, platform):
1081         m = Module()
1082
1083         mwid = self.o.z.m_width+2
1084         pe = PriorityEncoder(mwid)
1085         m.submodules.norm_pe = pe
1086
1087         of = Overflow()
1088         m.d.comb += self.o.roundz.eq(of.roundz)
1089
1090         m.submodules.norm1_out_z = self.o.z
1091         m.submodules.norm1_out_overflow = of
1092         m.submodules.norm1_in_z = self.i.z
1093         m.submodules.norm1_in_overflow = self.i.of
1094
1095         i = self.ispec()
1096         m.submodules.norm1_insel_z = i.z
1097         m.submodules.norm1_insel_overflow = i.of
1098
1099         espec = (len(i.z.e), True)
1100         ediff_n126 = Signal(espec, reset_less=True)
1101         msr = MultiShiftRMerge(mwid, espec)
1102         m.submodules.multishift_r = msr
1103
1104         m.d.comb += i.eq(self.i)
1105         # initialise out from in (overridden below)
1106         m.d.comb += self.o.z.eq(i.z)
1107         m.d.comb += of.eq(i.of)
1108         # normalisation increase/decrease conditions
1109         decrease = Signal(reset_less=True)
1110         increase = Signal(reset_less=True)
1111         m.d.comb += decrease.eq(i.z.m_msbzero & i.z.exp_gt_n126)
1112         m.d.comb += increase.eq(i.z.exp_lt_n126)
1113         # decrease exponent
1114         with m.If(~self.i.out_do_z):
1115             with m.If(decrease):
1116                 # *sigh* not entirely obvious: count leading zeros (clz)
1117                 # with a PriorityEncoder: to find from the MSB
1118                 # we reverse the order of the bits.
1119                 temp_m = Signal(mwid, reset_less=True)
1120                 temp_s = Signal(mwid+1, reset_less=True)
1121                 clz = Signal((len(i.z.e), True), reset_less=True)
1122                 # make sure that the amount to decrease by does NOT
1123                 # go below the minimum non-INF/NaN exponent
1124                 limclz = Mux(i.z.exp_sub_n126 > pe.o, pe.o,
1125                              i.z.exp_sub_n126)
1126                 m.d.comb += [
1127                     # cat round and guard bits back into the mantissa
1128                     temp_m.eq(Cat(i.of.round_bit, i.of.guard, i.z.m)),
1129                     pe.i.eq(temp_m[::-1]),          # inverted
1130                     clz.eq(limclz),                 # count zeros from MSB down
1131                     temp_s.eq(temp_m << clz),       # shift mantissa UP
1132                     self.o.z.e.eq(i.z.e - clz),  # DECREASE exponent
1133                     self.o.z.m.eq(temp_s[2:]),    # exclude bits 0&1
1134                     of.m0.eq(temp_s[2]),          # copy of mantissa[0]
1135                     # overflow in bits 0..1: got shifted too (leave sticky)
1136                     of.guard.eq(temp_s[1]),       # guard
1137                     of.round_bit.eq(temp_s[0]),   # round
1138                 ]
1139             # increase exponent
1140             with m.Elif(increase):
1141                 temp_m = Signal(mwid+1, reset_less=True)
1142                 m.d.comb += [
1143                     temp_m.eq(Cat(i.of.sticky, i.of.round_bit, i.of.guard,
1144                                   i.z.m)),
1145                     ediff_n126.eq(i.z.N126 - i.z.e),
1146                     # connect multi-shifter to inp/out mantissa (and ediff)
1147                     msr.inp.eq(temp_m),
1148                     msr.diff.eq(ediff_n126),
1149                     self.o.z.m.eq(msr.m[3:]),
1150                     of.m0.eq(temp_s[3]),   # copy of mantissa[0]
1151                     # overflow in bits 0..1: got shifted too (leave sticky)
1152                     of.guard.eq(temp_s[2]),     # guard
1153                     of.round_bit.eq(temp_s[1]), # round
1154                     of.sticky.eq(temp_s[0]),    # sticky
1155                     self.o.z.e.eq(i.z.e + ediff_n126),
1156                 ]
1157
1158         m.d.comb += self.o.mid.eq(self.i.mid)
1159         m.d.comb += self.o.out_do_z.eq(self.i.out_do_z)
1160         m.d.comb += self.o.oz.eq(self.i.oz)
1161
1162         return m
1163
1164
1165 class FPNorm1ModMulti:
1166
1167     def __init__(self, width, single_cycle=True):
1168         self.width = width
1169         self.in_select = Signal(reset_less=True)
1170         self.in_z = FPNumBase(width, False)
1171         self.in_of = Overflow()
1172         self.temp_z = FPNumBase(width, False)
1173         self.temp_of = Overflow()
1174         self.out_z = FPNumBase(width, False)
1175         self.out_of = Overflow()
1176
1177     def elaborate(self, platform):
1178         m = Module()
1179
1180         m.submodules.norm1_out_z = self.out_z
1181         m.submodules.norm1_out_overflow = self.out_of
1182         m.submodules.norm1_temp_z = self.temp_z
1183         m.submodules.norm1_temp_of = self.temp_of
1184         m.submodules.norm1_in_z = self.in_z
1185         m.submodules.norm1_in_overflow = self.in_of
1186
1187         in_z = FPNumBase(self.width, False)
1188         in_of = Overflow()
1189         m.submodules.norm1_insel_z = in_z
1190         m.submodules.norm1_insel_overflow = in_of
1191
1192         # select which of temp or in z/of to use
1193         with m.If(self.in_select):
1194             m.d.comb += in_z.eq(self.in_z)
1195             m.d.comb += in_of.eq(self.in_of)
1196         with m.Else():
1197             m.d.comb += in_z.eq(self.temp_z)
1198             m.d.comb += in_of.eq(self.temp_of)
1199         # initialise out from in (overridden below)
1200         m.d.comb += self.out_z.eq(in_z)
1201         m.d.comb += self.out_of.eq(in_of)
1202         # normalisation increase/decrease conditions
1203         decrease = Signal(reset_less=True)
1204         increase = Signal(reset_less=True)
1205         m.d.comb += decrease.eq(in_z.m_msbzero & in_z.exp_gt_n126)
1206         m.d.comb += increase.eq(in_z.exp_lt_n126)
1207         m.d.comb += self.out_norm.eq(decrease | increase) # loop-end
1208         # decrease exponent
1209         with m.If(decrease):
1210             m.d.comb += [
1211                 self.out_z.e.eq(in_z.e - 1),  # DECREASE exponent
1212                 self.out_z.m.eq(in_z.m << 1), # shift mantissa UP
1213                 self.out_z.m[0].eq(in_of.guard), # steal guard (was tot[2])
1214                 self.out_of.guard.eq(in_of.round_bit), # round (was tot[1])
1215                 self.out_of.round_bit.eq(0),        # reset round bit
1216                 self.out_of.m0.eq(in_of.guard),
1217             ]
1218         # increase exponent
1219         with m.Elif(increase):
1220             m.d.comb += [
1221                 self.out_z.e.eq(in_z.e + 1),  # INCREASE exponent
1222                 self.out_z.m.eq(in_z.m >> 1), # shift mantissa DOWN
1223                 self.out_of.guard.eq(in_z.m[0]),
1224                 self.out_of.m0.eq(in_z.m[1]),
1225                 self.out_of.round_bit.eq(in_of.guard),
1226                 self.out_of.sticky.eq(in_of.sticky | in_of.round_bit)
1227             ]
1228
1229         return m
1230
1231
1232 class FPNorm1Single(FPState):
1233
1234     def __init__(self, width, id_wid, single_cycle=True):
1235         FPState.__init__(self, "normalise_1")
1236         self.mod = FPNorm1ModSingle(width)
1237         self.o = self.ospec()
1238         self.out_z = FPNumBase(width, False)
1239         self.out_roundz = Signal(reset_less=True)
1240
1241     def ispec(self):
1242         return self.mod.ispec()
1243
1244     def ospec(self):
1245         return self.mod.ospec()
1246
1247     def setup(self, m, i):
1248         """ links module to inputs and outputs
1249         """
1250         self.mod.setup(m, i)
1251
1252     def action(self, m):
1253         m.next = "round"
1254
1255
1256 class FPNorm1Multi(FPState):
1257
1258     def __init__(self, width, id_wid):
1259         FPState.__init__(self, "normalise_1")
1260         self.mod = FPNorm1ModMulti(width)
1261         self.stb = Signal(reset_less=True)
1262         self.ack = Signal(reset=0, reset_less=True)
1263         self.out_norm = Signal(reset_less=True)
1264         self.in_accept = Signal(reset_less=True)
1265         self.temp_z = FPNumBase(width)
1266         self.temp_of = Overflow()
1267         self.out_z = FPNumBase(width)
1268         self.out_roundz = Signal(reset_less=True)
1269
1270     def setup(self, m, in_z, in_of, norm_stb):
1271         """ links module to inputs and outputs
1272         """
1273         self.mod.setup(m, in_z, in_of, norm_stb,
1274                        self.in_accept, self.temp_z, self.temp_of,
1275                        self.out_z, self.out_norm)
1276
1277         m.d.comb += self.stb.eq(norm_stb)
1278         m.d.sync += self.ack.eq(0) # sets to zero when not in normalise_1 state
1279
1280     def action(self, m):
1281         m.d.comb += self.in_accept.eq((~self.ack) & (self.stb))
1282         m.d.sync += self.temp_of.eq(self.mod.out_of)
1283         m.d.sync += self.temp_z.eq(self.out_z)
1284         with m.If(self.out_norm):
1285             with m.If(self.in_accept):
1286                 m.d.sync += [
1287                     self.ack.eq(1),
1288                 ]
1289             with m.Else():
1290                 m.d.sync += self.ack.eq(0)
1291         with m.Else():
1292             # normalisation not required (or done).
1293             m.next = "round"
1294             m.d.sync += self.ack.eq(1)
1295             m.d.sync += self.out_roundz.eq(self.mod.out_of.roundz)
1296
1297
1298 class FPNormToPack(FPState):
1299
1300     def __init__(self, width, id_wid):
1301         FPState.__init__(self, "normalise_1")
1302         self.id_wid = id_wid
1303         self.width = width
1304
1305     def ispec(self):
1306         return FPAddStage1Data(self.width, self.id_wid) # Norm1ModSingle ispec
1307
1308     def ospec(self):
1309         return FPPackData(self.width, self.id_wid) # FPPackMod ospec
1310
1311     def setup(self, m, i):
1312         """ links module to inputs and outputs
1313         """
1314
1315         # Normalisation, Rounding Corrections, Pack - in a chain
1316         nmod = FPNorm1ModSingle(self.width, self.id_wid)
1317         rmod = FPRoundMod(self.width, self.id_wid)
1318         cmod = FPCorrectionsMod(self.width, self.id_wid)
1319         pmod = FPPackMod(self.width, self.id_wid)
1320         chain = StageChain([nmod, rmod, cmod, pmod])
1321         chain.setup(m, i)
1322         self.out_z = pmod.ospec()
1323
1324         m.d.sync += self.out_z.mid.eq(pmod.o.mid)
1325         m.d.sync += self.out_z.z.v.eq(pmod.o.z.v) # outputs packed result
1326
1327     def action(self, m):
1328         m.next = "pack_put_z"
1329
1330
1331 class FPRoundData:
1332
1333     def __init__(self, width, id_wid):
1334         self.z = FPNumBase(width, False)
1335         self.out_do_z = Signal(reset_less=True)
1336         self.oz = Signal(width, reset_less=True)
1337         self.mid = Signal(id_wid, reset_less=True)
1338
1339     def eq(self, i):
1340         return [self.z.eq(i.z), self.out_do_z.eq(i.out_do_z), self.oz.eq(i.oz),
1341                 self.mid.eq(i.mid)]
1342
1343
1344 class FPRoundMod:
1345
1346     def __init__(self, width, id_wid):
1347         self.width = width
1348         self.id_wid = id_wid
1349         self.i = self.ispec()
1350         self.out_z = self.ospec()
1351
1352     def ispec(self):
1353         return FPNorm1Data(self.width, self.id_wid)
1354
1355     def ospec(self):
1356         return FPRoundData(self.width, self.id_wid)
1357
1358     def process(self, i):
1359         return self.out_z
1360
1361     def setup(self, m, i):
1362         m.submodules.roundz = self
1363         m.d.comb += self.i.eq(i)
1364
1365     def elaborate(self, platform):
1366         m = Module()
1367         m.d.comb += self.out_z.eq(self.i) # copies mid, z, out_do_z
1368         with m.If(~self.i.out_do_z):
1369             with m.If(self.i.roundz):
1370                 m.d.comb += self.out_z.z.m.eq(self.i.z.m + 1) # mantissa up
1371                 with m.If(self.i.z.m == self.i.z.m1s): # all 1s
1372                     m.d.comb += self.out_z.z.e.eq(self.i.z.e + 1) # exponent up
1373
1374         return m
1375
1376
1377 class FPRound(FPState):
1378
1379     def __init__(self, width, id_wid):
1380         FPState.__init__(self, "round")
1381         self.mod = FPRoundMod(width)
1382         self.out_z = self.ospec()
1383
1384     def ispec(self):
1385         return self.mod.ispec()
1386
1387     def ospec(self):
1388         return self.mod.ospec()
1389
1390     def setup(self, m, i):
1391         """ links module to inputs and outputs
1392         """
1393         self.mod.setup(m, i)
1394
1395         self.idsync(m)
1396         m.d.sync += self.out_z.eq(self.mod.out_z)
1397         m.d.sync += self.out_z.mid.eq(self.mod.o.mid)
1398
1399     def action(self, m):
1400         m.next = "corrections"
1401
1402
1403 class FPCorrectionsMod:
1404
1405     def __init__(self, width, id_wid):
1406         self.width = width
1407         self.id_wid = id_wid
1408         self.i = self.ispec()
1409         self.out_z = self.ospec()
1410
1411     def ispec(self):
1412         return FPRoundData(self.width, self.id_wid)
1413
1414     def ospec(self):
1415         return FPRoundData(self.width, self.id_wid)
1416
1417     def process(self, i):
1418         return self.out_z
1419
1420     def setup(self, m, i):
1421         """ links module to inputs and outputs
1422         """
1423         m.submodules.corrections = self
1424         m.d.comb += self.i.eq(i)
1425
1426     def elaborate(self, platform):
1427         m = Module()
1428         m.submodules.corr_in_z = self.i.z
1429         m.submodules.corr_out_z = self.out_z.z
1430         m.d.comb += self.out_z.eq(self.i) # copies mid, z, out_do_z
1431         with m.If(~self.i.out_do_z):
1432             with m.If(self.i.z.is_denormalised):
1433                 m.d.comb += self.out_z.z.e.eq(self.i.z.N127)
1434         return m
1435
1436
1437 class FPCorrections(FPState):
1438
1439     def __init__(self, width, id_wid):
1440         FPState.__init__(self, "corrections")
1441         self.mod = FPCorrectionsMod(width)
1442         self.out_z = self.ospec()
1443
1444     def ispec(self):
1445         return self.mod.ispec()
1446
1447     def ospec(self):
1448         return self.mod.ospec()
1449
1450     def setup(self, m, in_z):
1451         """ links module to inputs and outputs
1452         """
1453         self.mod.setup(m, in_z)
1454
1455         m.d.sync += self.out_z.eq(self.mod.out_z)
1456         m.d.sync += self.out_z.mid.eq(self.mod.o.mid)
1457
1458     def action(self, m):
1459         m.next = "pack"
1460
1461
1462 class FPPackData:
1463
1464     def __init__(self, width, id_wid):
1465         self.z = FPNumOut(width, False)
1466         self.mid = Signal(id_wid, reset_less=True)
1467
1468     def eq(self, i):
1469         return [self.z.eq(i.z), self.mid.eq(i.mid)]
1470
1471
1472 class FPPackMod:
1473
1474     def __init__(self, width, id_wid):
1475         self.width = width
1476         self.id_wid = id_wid
1477         self.i = self.ispec()
1478         self.o = self.ospec()
1479
1480     def ispec(self):
1481         return FPRoundData(self.width, self.id_wid)
1482
1483     def ospec(self):
1484         return FPPackData(self.width, self.id_wid)
1485
1486     def process(self, i):
1487         return self.o
1488
1489     def setup(self, m, in_z):
1490         """ links module to inputs and outputs
1491         """
1492         m.submodules.pack = self
1493         m.d.comb += self.i.eq(in_z)
1494
1495     def elaborate(self, platform):
1496         m = Module()
1497         m.submodules.pack_in_z = self.i.z
1498         m.d.comb += self.o.mid.eq(self.i.mid)
1499         with m.If(~self.i.out_do_z):
1500             with m.If(self.i.z.is_overflowed):
1501                 m.d.comb += self.o.z.inf(self.i.z.s)
1502             with m.Else():
1503                 m.d.comb += self.o.z.create(self.i.z.s, self.i.z.e, self.i.z.m)
1504         with m.Else():
1505             m.d.comb += self.o.z.v.eq(self.i.oz)
1506         return m
1507
1508
1509 class FPPack(FPState):
1510
1511     def __init__(self, width, id_wid):
1512         FPState.__init__(self, "pack")
1513         self.mod = FPPackMod(width)
1514         self.out_z = self.ospec()
1515
1516     def ispec(self):
1517         return self.mod.ispec()
1518
1519     def ospec(self):
1520         return self.mod.ospec()
1521
1522     def setup(self, m, in_z):
1523         """ links module to inputs and outputs
1524         """
1525         self.mod.setup(m, in_z)
1526
1527         m.d.sync += self.out_z.v.eq(self.mod.out_z.v)
1528         m.d.sync += self.out_z.mid.eq(self.mod.o.mid)
1529
1530     def action(self, m):
1531         m.next = "pack_put_z"
1532
1533
1534 class FPPutZ(FPState):
1535
1536     def __init__(self, state, in_z, out_z, in_mid, out_mid, to_state=None):
1537         FPState.__init__(self, state)
1538         if to_state is None:
1539             to_state = "get_ops"
1540         self.to_state = to_state
1541         self.in_z = in_z
1542         self.out_z = out_z
1543         self.in_mid = in_mid
1544         self.out_mid = out_mid
1545
1546     def action(self, m):
1547         if self.in_mid is not None:
1548             m.d.sync += self.out_mid.eq(self.in_mid)
1549         m.d.sync += [
1550           self.out_z.z.v.eq(self.in_z.v)
1551         ]
1552         with m.If(self.out_z.z.stb & self.out_z.z.ack):
1553             m.d.sync += self.out_z.z.stb.eq(0)
1554             m.next = self.to_state
1555         with m.Else():
1556             m.d.sync += self.out_z.z.stb.eq(1)
1557
1558
1559 class FPPutZIdx(FPState):
1560
1561     def __init__(self, state, in_z, out_zs, in_mid, to_state=None):
1562         FPState.__init__(self, state)
1563         if to_state is None:
1564             to_state = "get_ops"
1565         self.to_state = to_state
1566         self.in_z = in_z
1567         self.out_zs = out_zs
1568         self.in_mid = in_mid
1569
1570     def action(self, m):
1571         outz_stb = Signal(reset_less=True)
1572         outz_ack = Signal(reset_less=True)
1573         m.d.comb += [outz_stb.eq(self.out_zs[self.in_mid].stb),
1574                      outz_ack.eq(self.out_zs[self.in_mid].ack),
1575                     ]
1576         m.d.sync += [
1577           self.out_zs[self.in_mid].v.eq(self.in_z.v)
1578         ]
1579         with m.If(outz_stb & outz_ack):
1580             m.d.sync += self.out_zs[self.in_mid].stb.eq(0)
1581             m.next = self.to_state
1582         with m.Else():
1583             m.d.sync += self.out_zs[self.in_mid].stb.eq(1)
1584
1585 class FPADDBaseData:
1586
1587     def __init__(self, width, id_wid):
1588         self.width = width
1589         self.id_wid = id_wid
1590         self.a  = Signal(width)
1591         self.b  = Signal(width)
1592         self.mid = Signal(id_wid, reset_less=True)
1593
1594     def eq(self, i):
1595         return [self.a.eq(i.a), self.b.eq(i.b), self.mid.eq(i.mid)]
1596
1597
1598 class FPOpData:
1599     def __init__(self, width, id_wid):
1600         self.z = FPOp(width)
1601         self.mid = Signal(id_wid, reset_less=True)
1602
1603     def eq(self, i):
1604         return [self.z.eq(i.z), self.mid.eq(i.mid)]
1605
1606
1607 class FPADDBaseMod:
1608
1609     def __init__(self, width, id_wid=None, single_cycle=False, compact=True):
1610         """ IEEE754 FP Add
1611
1612             * width: bit-width of IEEE754.  supported: 16, 32, 64
1613             * id_wid: an identifier that is sync-connected to the input
1614             * single_cycle: True indicates each stage to complete in 1 clock
1615             * compact: True indicates a reduced number of stages
1616         """
1617         self.width = width
1618         self.id_wid = id_wid
1619         self.single_cycle = single_cycle
1620         self.compact = compact
1621
1622         self.in_t = Trigger()
1623         self.i = self.ispec()
1624         self.o = self.ospec()
1625
1626         self.states = []
1627
1628     def ispec(self):
1629         return FPADDBaseData(self.width, self.id_wid)
1630
1631     def ospec(self):
1632         return FPOpData(self.width, self.id_wid)
1633
1634     def add_state(self, state):
1635         self.states.append(state)
1636         return state
1637
1638     def get_fragment(self, platform=None):
1639         """ creates the HDL code-fragment for FPAdd
1640         """
1641         m = Module()
1642         m.submodules.out_z = self.o.z
1643         m.submodules.in_t = self.in_t
1644         if self.compact:
1645             self.get_compact_fragment(m, platform)
1646         else:
1647             self.get_longer_fragment(m, platform)
1648
1649         with m.FSM() as fsm:
1650
1651             for state in self.states:
1652                 with m.State(state.state_from):
1653                     state.action(m)
1654
1655         return m
1656
1657     def get_longer_fragment(self, m, platform=None):
1658
1659         get = self.add_state(FPGet2Op("get_ops", "special_cases",
1660                                       self.width))
1661         get.setup(m, self.i, self.in_t.stb, self.in_t.ack)
1662         a = get.out_op1
1663         b = get.out_op2
1664
1665         sc = self.add_state(FPAddSpecialCases(self.width, self.id_wid))
1666         sc.setup(m, a, b, self.in_mid)
1667
1668         dn = self.add_state(FPAddDeNorm(self.width, self.id_wid))
1669         dn.setup(m, a, b, sc.in_mid)
1670
1671         if self.single_cycle:
1672             alm = self.add_state(FPAddAlignSingle(self.width, self.id_wid))
1673             alm.setup(m, dn.out_a, dn.out_b, dn.in_mid)
1674         else:
1675             alm = self.add_state(FPAddAlignMulti(self.width, self.id_wid))
1676             alm.setup(m, dn.out_a, dn.out_b, dn.in_mid)
1677
1678         add0 = self.add_state(FPAddStage0(self.width, self.id_wid))
1679         add0.setup(m, alm.out_a, alm.out_b, alm.in_mid)
1680
1681         add1 = self.add_state(FPAddStage1(self.width, self.id_wid))
1682         add1.setup(m, add0.out_tot, add0.out_z, add0.in_mid)
1683
1684         if self.single_cycle:
1685             n1 = self.add_state(FPNorm1Single(self.width, self.id_wid))
1686             n1.setup(m, add1.out_z, add1.out_of, add0.in_mid)
1687         else:
1688             n1 = self.add_state(FPNorm1Multi(self.width, self.id_wid))
1689             n1.setup(m, add1.out_z, add1.out_of, add1.norm_stb, add0.in_mid)
1690
1691         rn = self.add_state(FPRound(self.width, self.id_wid))
1692         rn.setup(m, n1.out_z, n1.out_roundz, n1.in_mid)
1693
1694         cor = self.add_state(FPCorrections(self.width, self.id_wid))
1695         cor.setup(m, rn.out_z, rn.in_mid)
1696
1697         pa = self.add_state(FPPack(self.width, self.id_wid))
1698         pa.setup(m, cor.out_z, rn.in_mid)
1699
1700         ppz = self.add_state(FPPutZ("pack_put_z", pa.out_z, self.out_z,
1701                                     pa.in_mid, self.out_mid))
1702
1703         pz = self.add_state(FPPutZ("put_z", sc.out_z, self.out_z,
1704                                     pa.in_mid, self.out_mid))
1705
1706     def get_compact_fragment(self, m, platform=None):
1707
1708         get = self.add_state(FPGet2Op("get_ops", "special_cases",
1709                                       self.width, self.id_wid))
1710         get.setup(m, self.i, self.in_t.stb, self.in_t.ack)
1711
1712         sc = self.add_state(FPAddSpecialCasesDeNorm(self.width, self.id_wid))
1713         sc.setup(m, get.o)
1714
1715         alm = self.add_state(FPAddAlignSingleAdd(self.width, self.id_wid))
1716         alm.setup(m, sc.o)
1717
1718         n1 = self.add_state(FPNormToPack(self.width, self.id_wid))
1719         n1.setup(m, alm.a1o)
1720
1721         ppz = self.add_state(FPPutZ("pack_put_z", n1.out_z.z, self.o,
1722                                     n1.out_z.mid, self.o.mid))
1723
1724         pz = self.add_state(FPPutZ("put_z", sc.out_z.z, self.o,
1725                                     sc.o.mid, self.o.mid))
1726
1727
1728 class FPADDBase(FPState):
1729
1730     def __init__(self, width, id_wid=None, single_cycle=False):
1731         """ IEEE754 FP Add
1732
1733             * width: bit-width of IEEE754.  supported: 16, 32, 64
1734             * id_wid: an identifier that is sync-connected to the input
1735             * single_cycle: True indicates each stage to complete in 1 clock
1736         """
1737         FPState.__init__(self, "fpadd")
1738         self.width = width
1739         self.single_cycle = single_cycle
1740         self.mod = FPADDBaseMod(width, id_wid, single_cycle)
1741         self.o = self.ospec()
1742
1743         self.in_t = Trigger()
1744         self.i = self.ispec()
1745
1746         self.z_done = Signal(reset_less=True) # connects to out_z Strobe
1747         self.in_accept = Signal(reset_less=True)
1748         self.add_stb = Signal(reset_less=True)
1749         self.add_ack = Signal(reset=0, reset_less=True)
1750
1751     def ispec(self):
1752         return self.mod.ispec()
1753
1754     def ospec(self):
1755         return self.mod.ospec()
1756
1757     def setup(self, m, i, add_stb, in_mid):
1758         m.d.comb += [self.i.eq(i),
1759                      self.mod.i.eq(self.i),
1760                      self.z_done.eq(self.mod.o.z.trigger),
1761                      #self.add_stb.eq(add_stb),
1762                      self.mod.in_t.stb.eq(self.in_t.stb),
1763                      self.in_t.ack.eq(self.mod.in_t.ack),
1764                      self.o.mid.eq(self.mod.o.mid),
1765                      self.o.z.v.eq(self.mod.o.z.v),
1766                      self.o.z.stb.eq(self.mod.o.z.stb),
1767                      self.mod.o.z.ack.eq(self.o.z.ack),
1768                     ]
1769
1770         m.d.sync += self.add_stb.eq(add_stb)
1771         m.d.sync += self.add_ack.eq(0) # sets to zero when not in active state
1772         m.d.sync += self.o.z.ack.eq(0) # likewise
1773         #m.d.sync += self.in_t.stb.eq(0)
1774
1775         m.submodules.fpadd = self.mod
1776
1777     def action(self, m):
1778
1779         # in_accept is set on incoming strobe HIGH and ack LOW.
1780         m.d.comb += self.in_accept.eq((~self.add_ack) & (self.add_stb))
1781
1782         #with m.If(self.in_t.ack):
1783         #    m.d.sync += self.in_t.stb.eq(0)
1784         with m.If(~self.z_done):
1785             # not done: test for accepting an incoming operand pair
1786             with m.If(self.in_accept):
1787                 m.d.sync += [
1788                     self.add_ack.eq(1), # acknowledge receipt...
1789                     self.in_t.stb.eq(1), # initiate add
1790                 ]
1791             with m.Else():
1792                 m.d.sync += [self.add_ack.eq(0),
1793                              self.in_t.stb.eq(0),
1794                              self.o.z.ack.eq(1),
1795                             ]
1796         with m.Else():
1797             # done: acknowledge, and write out id and value
1798             m.d.sync += [self.add_ack.eq(1),
1799                          self.in_t.stb.eq(0)
1800                         ]
1801             m.next = "put_z"
1802
1803             return
1804
1805             if self.in_mid is not None:
1806                 m.d.sync += self.out_mid.eq(self.mod.out_mid)
1807
1808             m.d.sync += [
1809               self.out_z.v.eq(self.mod.out_z.v)
1810             ]
1811             # move to output state on detecting z ack
1812             with m.If(self.out_z.trigger):
1813                 m.d.sync += self.out_z.stb.eq(0)
1814                 m.next = "put_z"
1815             with m.Else():
1816                 m.d.sync += self.out_z.stb.eq(1)
1817
1818
1819 class ResArray:
1820     def __init__(self, width, id_wid):
1821         self.width = width
1822         self.id_wid = id_wid
1823         res = []
1824         for i in range(rs_sz):
1825             out_z = FPOp(width)
1826             out_z.name = "out_z_%d" % i
1827             res.append(out_z)
1828         self.res = Array(res)
1829         self.in_z = FPOp(width)
1830         self.in_mid = Signal(self.id_wid, reset_less=True)
1831
1832     def setup(self, m, in_z, in_mid):
1833         m.d.comb += [self.in_z.eq(in_z),
1834                      self.in_mid.eq(in_mid)]
1835
1836     def get_fragment(self, platform=None):
1837         """ creates the HDL code-fragment for FPAdd
1838         """
1839         m = Module()
1840         m.submodules.res_in_z = self.in_z
1841         m.submodules += self.res
1842
1843         return m
1844
1845     def ports(self):
1846         res = []
1847         for z in self.res:
1848             res += z.ports()
1849         return res
1850
1851
1852 class FPADD(FPID):
1853     """ FPADD: stages as follows:
1854
1855         FPGetOp (a)
1856            |
1857         FPGetOp (b)
1858            |
1859         FPAddBase---> FPAddBaseMod
1860            |            |
1861         PutZ          GetOps->Specials->Align->Add1/2->Norm->Round/Pack->PutZ
1862
1863         FPAddBase is tricky: it is both a stage and *has* stages.
1864         Connection to FPAddBaseMod therefore requires an in stb/ack
1865         and an out stb/ack.  Just as with Add1-Norm1 interaction, FPGetOp
1866         needs to be the thing that raises the incoming stb.
1867     """
1868
1869     def __init__(self, width, id_wid=None, single_cycle=False, rs_sz=2):
1870         """ IEEE754 FP Add
1871
1872             * width: bit-width of IEEE754.  supported: 16, 32, 64
1873             * id_wid: an identifier that is sync-connected to the input
1874             * single_cycle: True indicates each stage to complete in 1 clock
1875         """
1876         self.width = width
1877         self.id_wid = id_wid
1878         self.single_cycle = single_cycle
1879
1880         #self.out_z = FPOp(width)
1881         self.ids = FPID(id_wid)
1882
1883         rs = []
1884         for i in range(rs_sz):
1885             in_a  = FPOp(width)
1886             in_b  = FPOp(width)
1887             in_a.name = "in_a_%d" % i
1888             in_b.name = "in_b_%d" % i
1889             rs.append((in_a, in_b))
1890         self.rs = Array(rs)
1891
1892         res = []
1893         for i in range(rs_sz):
1894             out_z = FPOp(width)
1895             out_z.name = "out_z_%d" % i
1896             res.append(out_z)
1897         self.res = Array(res)
1898
1899         self.states = []
1900
1901     def add_state(self, state):
1902         self.states.append(state)
1903         return state
1904
1905     def get_fragment(self, platform=None):
1906         """ creates the HDL code-fragment for FPAdd
1907         """
1908         m = Module()
1909         m.submodules += self.rs
1910
1911         in_a = self.rs[0][0]
1912         in_b = self.rs[0][1]
1913
1914         geta = self.add_state(FPGetOp("get_a", "get_b",
1915                                       in_a, self.width))
1916         geta.setup(m, in_a)
1917         a = geta.out_op
1918
1919         getb = self.add_state(FPGetOp("get_b", "fpadd",
1920                                       in_b, self.width))
1921         getb.setup(m, in_b)
1922         b = getb.out_op
1923
1924         ab = FPADDBase(self.width, self.id_wid, self.single_cycle)
1925         ab = self.add_state(ab)
1926         abd = ab.ispec() # create an input spec object for FPADDBase
1927         m.d.sync += [abd.a.eq(a), abd.b.eq(b), abd.mid.eq(self.ids.in_mid)]
1928         ab.setup(m, abd, getb.out_decode, self.ids.in_mid)
1929         o = ab.o
1930
1931         pz = self.add_state(FPPutZIdx("put_z", o.z, self.res,
1932                                     o.mid, "get_a"))
1933
1934         with m.FSM() as fsm:
1935
1936             for state in self.states:
1937                 with m.State(state.state_from):
1938                     state.action(m)
1939
1940         return m
1941
1942
1943 if __name__ == "__main__":
1944     if True:
1945         alu = FPADD(width=32, id_wid=5, single_cycle=True)
1946         main(alu, ports=alu.rs[0][0].ports() + \
1947                         alu.rs[0][1].ports() + \
1948                         alu.res[0].ports() + \
1949                         [alu.ids.in_mid, alu.ids.out_mid])
1950     else:
1951         alu = FPADDBase(width=32, id_wid=5, single_cycle=True)
1952         main(alu, ports=[alu.in_a, alu.in_b] + \
1953                         alu.in_t.ports() + \
1954                         alu.out_z.ports() + \
1955                         [alu.in_mid, alu.out_mid])
1956
1957
1958     # works... but don't use, just do "python fname.py convert -t v"
1959     #print (verilog.convert(alu, ports=[
1960     #                        ports=alu.in_a.ports() + \
1961     #                              alu.in_b.ports() + \
1962     #                              alu.out_z.ports())