src/add/pipeline_example.py

   1 """ Example 5: Making use of PyRTL and Introspection. """
   2
   3 from nmigen import Module, Signal
   4 from nmigen.cli import main, verilog
   5
   6
   7 from pipeline import SimplePipeline
   8
   9
  10 class SimplePipelineExample(SimplePipeline):
  11     """ A very simple pipeline to show how registers are inferred. """
  12
  13     def __init__(self, pipe):
  14         SimplePipeline.__init__(self, pipe)
  15         self._loopback = Signal(4)
  16         self._setup()
  17
  18     def stage0(self):
  19         self.n = ~self._loopback
  20
  21     def stage1(self):
  22         self.n = self.n + 1
  23
  24     def stage2(self):
  25         self.n = self.n << 1
  26
  27     def stage3(self):
  28         self.n = ~self.n
  29
  30     def stage4(self):
  31         self._pipe.sync += self._loopback.eq(self.n + 3)
  32
  33 class PipeModule:
  34
  35     def __init__(self):
  36         self.m = Module()
  37         self.p = SimplePipelineExample(self.m.d)
  38
  39     def get_fragment(self, platform=None):
  40         return self.m
  41
  42 if __name__ == "__main__":
  43     example = PipeModule()
  44     main(example, ports=[
  45                     example.p._loopback,
  46         ])
  47
  48     print(verilog.convert(example, ports=[
  49                example.p._loopback,
  50              ]))