src/add/queue.py

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  25
  26 from nmigen import Module, Signal, Memory, Mux
  27 from nmigen.tools import bits_for
  28 from nmigen.cli import main
  29 from nmigen.lib.fifo import FIFOInterface
  30
  31 # translated from https://github.com/freechipsproject/chisel3/blob/a4a29e29c3f1eed18f851dcf10bdc845571dfcb6/src/main/scala/chisel3/util/Decoupled.scala#L185   # noqa
  32
  33
  34 class Queue(FIFOInterface):
  35     def __init__(self, width, depth, fwft=True, pipe=False):
  36         """ Queue (FIFO) with pipe mode and first-write fall-through capability
  37
  38             * width: width of Queue data in/out
  39             * depth: queue depth.  NOTE: may be set to 0 (this is ok)
  40             * fwft : first-write, fall-through mode (Chisel Queue "flow" mode)
  41             * pipe : pipe mode.  NOTE: this mode can cause unanticipated
  42                      problems.  when read is enabled, so is writeable.
  43                      therefore if read is enabled, the data ABSOLUTELY MUST
  44                      be read.
  45
  46             Attributes:
  47             * level: available free space (number of unread entries)
  48
  49             din  = enq_data, writable  = enq_ready, we = enq_valid
  50             dout = deq_data, re = deq_ready, readable = deq_valid
  51         """
  52         FIFOInterface.__init__(self, width, depth, fwft)
  53         self.pipe = pipe
  54         self.depth = depth
  55         self.level = Signal(bits_for(depth))
  56
  57     def elaborate(self, platform):
  58         m = Module()
  59
  60         # set up an SRAM.  XXX bug in Memory: cannot create SRAM of depth 1
  61         ram = Memory(self.width, self.depth if self.depth > 1 else 2)
  62         m.submodules.ram_read = ram_read = ram.read_port(synchronous=False)
  63         m.submodules.ram_write = ram_write = ram.write_port()
  64
  65         # convenience names
  66         p_o_ready = self.writable
  67         p_i_valid = self.we
  68         enq_data = self.din
  69
  70         n_o_valid = self.readable
  71         n_i_ready = self.re
  72         deq_data = self.dout
  73
  74         # intermediaries
  75         ptr_width = bits_for(self.depth - 1) if self.depth > 1 else 0
  76         enq_ptr = Signal(ptr_width) # cyclic pointer to "insert" point (wrport)
  77         deq_ptr = Signal(ptr_width) # cyclic pointer to "remove" point (rdport)
  78         maybe_full = Signal() # not reset_less (set by sync)
  79
  80         # temporaries
  81         do_enq = Signal(reset_less=True)
  82         do_deq = Signal(reset_less=True)
  83         ptr_diff = Signal(ptr_width)
  84         ptr_match = Signal(reset_less=True)
  85         empty = Signal(reset_less=True)
  86         full = Signal(reset_less=True)
  87         enq_max = Signal(reset_less=True)
  88         deq_max = Signal(reset_less=True)
  89
  90         m.d.comb += [ptr_match.eq(enq_ptr == deq_ptr), # read-ptr = write-ptr
  91                      ptr_diff.eq(enq_ptr - deq_ptr),
  92                      enq_max.eq(enq_ptr == self.depth - 1),
  93                      deq_max.eq(deq_ptr == self.depth - 1),
  94                      empty.eq(ptr_match & ~maybe_full),
  95                      full.eq(ptr_match & maybe_full),
  96                      do_enq.eq(p_o_ready & p_i_valid), # write conditions ok
  97                      do_deq.eq(n_i_ready & n_o_valid), # read conditions ok
  98
  99                      # set readable and writable (NOTE: see pipe mode below)
 100                      n_o_valid.eq(~empty), # cannot read if empty!
 101                      p_o_ready.eq(~full),  # cannot write if full!
 102
 103                      # set up memory and connect to input and output
 104                      ram_write.addr.eq(enq_ptr),
 105                      ram_write.data.eq(enq_data),
 106                      ram_write.en.eq(do_enq),
 107                      ram_read.addr.eq(deq_ptr),
 108                      deq_data.eq(ram_read.data) # NOTE: overridden in fwft mode
 109                     ]
 110
 111         # under write conditions, SRAM write-pointer moves on next clock
 112         with m.If(do_enq):
 113             m.d.sync += enq_ptr.eq(Mux(enq_max, 0, enq_ptr+1))
 114
 115         # under read conditions, SRAM read-pointer moves on next clock
 116         with m.If(do_deq):
 117             m.d.sync += deq_ptr.eq(Mux(deq_max, 0, deq_ptr+1))
 118
 119         # if read-but-not-write or write-but-not-read, maybe_full set
 120         with m.If(do_enq != do_deq):
 121             m.d.sync += maybe_full.eq(do_enq)
 122
 123         # first-word fall-through: same as "flow" parameter in Chisel3 Queue
 124         # basically instead of relying on the Memory characteristics (which
 125         # in FPGAs do not have write-through), then when the queue is empty
 126         # take the output directly from the input, i.e. *bypass* the SRAM.
 127         # this done combinatorially to give the exact same characteristics
 128         # as Memory "write-through"... without relying on a changing API
 129         if self.fwft:
 130             with m.If(p_i_valid):
 131                 m.d.comb += n_o_valid.eq(1)
 132             with m.If(empty):
 133                 m.d.comb += deq_data.eq(enq_data)
 134                 m.d.comb += do_deq.eq(0)
 135                 with m.If(n_i_ready):
 136                     m.d.comb += do_enq.eq(0)
 137
 138         # pipe mode: if next stage says it's ready (readable), we
 139         #            *must* declare the input ready (writeable).
 140         if self.pipe:
 141             with m.If(n_i_ready):
 142                 m.d.comb += p_o_ready.eq(1)
 143
 144         # set the count (available free space), optimise on power-of-two
 145         if self.depth == 1 << ptr_width:  # is depth a power of 2
 146             m.d.comb += self.level.eq(
 147                 Mux(maybe_full & ptr_match, self.depth, 0) | ptr_diff)
 148         else:
 149             m.d.comb += self.level.eq(Mux(ptr_match,
 150                                           Mux(maybe_full, self.depth, 0),
 151                                           Mux(deq_ptr > enq_ptr,
 152                                               self.depth + ptr_diff,
 153                                               ptr_diff)))
 154
 155         return m
 156
 157
 158 if __name__ == "__main__":
 159     reg_stage = Queue(1, 1, pipe=True)
 160     break_ready_chain_stage = Queue(1, 1, pipe=True, fwft=True)
 161     m = Module()
 162     ports = []
 163
 164     def queue_ports(queue, name_prefix):
 165         retval = []
 166         for name in ["level",
 167                      "dout",
 168                      "readable",
 169                      "writable"]:
 170             port = getattr(queue, name)
 171             signal = Signal(port.shape(), name=name_prefix+name)
 172             m.d.comb += signal.eq(port)
 173             retval.append(signal)
 174         for name in ["re",
 175                      "din",
 176                      "we"]:
 177             port = getattr(queue, name)
 178             signal = Signal(port.shape(), name=name_prefix+name)
 179             m.d.comb += port.eq(signal)
 180             retval.append(signal)
 181         return retval
 182     m.submodules.reg_stage = reg_stage
 183     ports += queue_ports(reg_stage, "reg_stage_")
 184     m.submodules.break_ready_chain_stage = break_ready_chain_stage
 185     ports += queue_ports(break_ready_chain_stage, "break_ready_chain_stage_")
 186     main(m, ports=ports)