src/ieee754/fpadd/add0.py

   1 # IEEE Floating Point Adder (Single Precision)
   2 # Copyright (C) Jonathan P Dawson 2013
   3 # 2013-12-12
   4
   5 from nmigen import Module, Signal, Cat, Elaboratable
   6 from nmigen.cli import main, verilog
   7
   8 from ieee754.fpcommon.fpbase import FPNumBase, FPNumBaseRecord
   9 from ieee754.fpcommon.fpbase import FPState
  10 from ieee754.fpcommon.denorm import FPSCData
  11 from ieee754.fpcommon.getop import FPBaseData
  12
  13
  14 class FPAddStage0Data:
  15
  16     def __init__(self, width, pspec):
  17         self.z = FPNumBaseRecord(width, False)
  18         self.out_do_z = Signal(reset_less=True)
  19         self.oz = Signal(width, reset_less=True)
  20         self.tot = Signal(self.z.m_width + 4, reset_less=True)
  21         self.ctx = FPBaseData(width, pspec)
  22         self.muxid = self.ctx.muxid
  23
  24     def eq(self, i):
  25         return [self.z.eq(i.z), self.out_do_z.eq(i.out_do_z), self.oz.eq(i.oz),
  26                 self.tot.eq(i.tot), self.ctx.eq(i.ctx)]
  27
  28
  29 class FPAddStage0Mod(Elaboratable):
  30
  31     def __init__(self, width, pspec):
  32         self.width = width
  33         self.pspec = pspec
  34         self.i = self.ispec()
  35         self.o = self.ospec()
  36
  37     def ispec(self):
  38         return FPSCData(self.width, self.pspec, True)
  39
  40     def ospec(self):
  41         return FPAddStage0Data(self.width, self.pspec)
  42
  43     def process(self, i):
  44         return self.o
  45
  46     def setup(self, m, i):
  47         """ links module to inputs and outputs
  48         """
  49         m.submodules.add0 = self
  50         m.d.comb += self.i.eq(i)
  51
  52     def elaborate(self, platform):
  53         m = Module()
  54         #m.submodules.add0_in_a = self.i.a
  55         #m.submodules.add0_in_b = self.i.b
  56         #m.submodules.add0_out_z = self.o.z
  57
  58         # store intermediate tests (and zero-extended mantissas)
  59         seq = Signal(reset_less=True)
  60         mge = Signal(reset_less=True)
  61         am0 = Signal(len(self.i.a.m)+1, reset_less=True)
  62         bm0 = Signal(len(self.i.b.m)+1, reset_less=True)
  63         m.d.comb += [seq.eq(self.i.a.s == self.i.b.s),
  64                      mge.eq(self.i.a.m >= self.i.b.m),
  65                      am0.eq(Cat(self.i.a.m, 0)),
  66                      bm0.eq(Cat(self.i.b.m, 0))
  67                     ]
  68         # same-sign (both negative or both positive) add mantissas
  69         with m.If(~self.i.out_do_z):
  70             m.d.comb += self.o.z.e.eq(self.i.a.e)
  71             with m.If(seq):
  72                 m.d.comb += [
  73                     self.o.tot.eq(am0 + bm0),
  74                     self.o.z.s.eq(self.i.a.s)
  75                 ]
  76             # a mantissa greater than b, use a
  77             with m.Elif(mge):
  78                 m.d.comb += [
  79                     self.o.tot.eq(am0 - bm0),
  80                     self.o.z.s.eq(self.i.a.s)
  81                 ]
  82             # b mantissa greater than a, use b
  83             with m.Else():
  84                 m.d.comb += [
  85                     self.o.tot.eq(bm0 - am0),
  86                     self.o.z.s.eq(self.i.b.s)
  87             ]
  88
  89         m.d.comb += self.o.oz.eq(self.i.oz)
  90         m.d.comb += self.o.out_do_z.eq(self.i.out_do_z)
  91         m.d.comb += self.o.ctx.eq(self.i.ctx)
  92         return m
  93
  94
  95 class FPAddStage0(FPState):
  96     """ First stage of add.  covers same-sign (add) and subtract
  97         special-casing when mantissas are greater or equal, to
  98         give greatest accuracy.
  99     """
 100
 101     def __init__(self, width, pspec):
 102         FPState.__init__(self, "add_0")
 103         self.mod = FPAddStage0Mod(width)
 104         self.o = self.mod.ospec()
 105
 106     def setup(self, m, i):
 107         """ links module to inputs and outputs
 108         """
 109         self.mod.setup(m, i)
 110
 111         # NOTE: these could be done as combinatorial (merge add0+add1)
 112         m.d.sync += self.o.eq(self.mod.o)
 113
 114     def action(self, m):
 115         m.next = "add_1"