src/ieee754/fpadd/add1.py

   1 """IEEE754 Floating Point Multiplier Pipeline
   2
   3 Copyright (C) 2019 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
   4
   5 """
   6
   7 from nmigen import Module, Signal, Elaboratable
   8 from nmigen.cli import main, verilog
   9 from math import log
  10
  11 from ieee754.fpcommon.postcalc import FPAddStage1Data
  12 from ieee754.fpadd.add0 import FPAddStage0Data
  13
  14
  15 class FPAddStage1Mod(Elaboratable):
  16     """ Second stage of add: preparation for normalisation.
  17         detects when tot sum is too big (tot[27] is kinda a carry bit)
  18     """
  19
  20     def __init__(self, pspec):
  21         self.pspec = pspec
  22         self.i = self.ispec()
  23         self.o = self.ospec()
  24
  25     def ispec(self):
  26         return FPAddStage0Data(self.pspec)
  27
  28     def ospec(self):
  29         return FPAddStage1Data(self.pspec)
  30
  31     def process(self, i):
  32         return self.o
  33
  34     def setup(self, m, i):
  35         """ links module to inputs and outputs
  36         """
  37         m.submodules.add1 = self
  38         m.d.comb += self.i.eq(i)
  39
  40     def elaborate(self, platform):
  41         m = Module()
  42         comb = m.d.comb
  43
  44         comb += self.o.z.eq(self.i.z)
  45         # tot[-1] (MSB) gets set when the sum overflows. shift result down
  46         with m.If(~self.i.out_do_z):
  47             with m.If(self.i.tot[-1]):
  48                 comb += [
  49                     self.o.z.m.eq(self.i.tot[4:]),
  50                     self.o.of.m0.eq(self.i.tot[4]),
  51                     self.o.of.guard.eq(self.i.tot[3]),
  52                     self.o.of.round_bit.eq(self.i.tot[2]),
  53                     self.o.of.sticky.eq(self.i.tot[1] | self.i.tot[0]),
  54                     self.o.z.e.eq(self.i.z.e + 1)
  55             ]
  56             # tot[-1] (MSB) zero case
  57             with m.Else():
  58                 comb += [
  59                     self.o.z.m.eq(self.i.tot[3:]),
  60                     self.o.of.m0.eq(self.i.tot[3]),
  61                     self.o.of.guard.eq(self.i.tot[2]),
  62                     self.o.of.round_bit.eq(self.i.tot[1]),
  63                     self.o.of.sticky.eq(self.i.tot[0])
  64             ]
  65
  66         comb += self.o.out_do_z.eq(self.i.out_do_z)
  67         comb += self.o.oz.eq(self.i.oz)
  68         comb += self.o.ctx.eq(self.i.ctx)
  69
  70         return m