src/ieee754/fpadd/add1.py

   1 """IEEE754 Floating Point Multiplier Pipeline
   2
   3 Copyright (C) 2019 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
   4
   5 """
   6
   7 from nmigen import Module, Signal
   8 from nmigen.cli import main, verilog
   9 from math import log
  10
  11 from nmutil.pipemodbase import PipeModBase
  12 from ieee754.fpcommon.postcalc import FPAddStage1Data
  13 from ieee754.fpadd.add0 import FPAddStage0Data
  14
  15
  16 class FPAddStage1Mod(PipeModBase):
  17     """ Second stage of add: preparation for normalisation.
  18         detects when tot sum is too big (tot[27] is kinda a carry bit)
  19     """
  20
  21     def __init__(self, pspec):
  22         super().__init__(pspec, "add1")
  23
  24     def ispec(self):
  25         return FPAddStage0Data(self.pspec)
  26
  27     def ospec(self):
  28         return FPAddStage1Data(self.pspec)
  29
  30     def elaborate(self, platform):
  31         m = Module()
  32         comb = m.d.comb
  33
  34         comb += self.o.z.eq(self.i.z)
  35         # tot[-1] (MSB) gets set when the sum overflows. shift result down
  36         with m.If(~self.i.out_do_z):
  37             with m.If(self.i.tot[-1]):
  38                 comb += [
  39                     self.o.z.m.eq(self.i.tot[4:]),
  40                     self.o.of.m0.eq(self.i.tot[4]),
  41                     self.o.of.guard.eq(self.i.tot[3]),
  42                     self.o.of.round_bit.eq(self.i.tot[2]),
  43                     self.o.of.sticky.eq(self.i.tot[1] | self.i.tot[0]),
  44                     self.o.z.e.eq(self.i.z.e + 1)
  45             ]
  46             # tot[-1] (MSB) zero case
  47             with m.Else():
  48                 comb += [
  49                     self.o.z.m.eq(self.i.tot[3:]),
  50                     self.o.of.m0.eq(self.i.tot[3]),
  51                     self.o.of.guard.eq(self.i.tot[2]),
  52                     self.o.of.round_bit.eq(self.i.tot[1]),
  53                     self.o.of.sticky.eq(self.i.tot[0])
  54             ]
  55
  56         comb += self.o.out_do_z.eq(self.i.out_do_z)
  57         comb += self.o.oz.eq(self.i.oz)
  58         comb += self.o.ctx.eq(self.i.ctx)
  59
  60         return m