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[ieee754fpu.git] / src / ieee754 / fpcommon / exphigh.py
1 # IEEE Floating Point Adder (Single Precision)
2 # Copyright (C) Jonathan P Dawson 2013
3 # 2013-12-12
4
5 from nmigen import Module, Signal, Elaboratable
6 from nmigen.cli import main, verilog
7
8 from ieee754.fpcommon.fpbase import MultiShiftRMerge
9
10
11 class FPEXPHigh(Elaboratable):
12
13 def __init__(self, m_width, e_width):
14 self.m_width = m_width
15 self.e_width = e_width
16 self.ediff = Signal((e_width, True), reset_less=True)
17
18 self.m_in = Signal(m_width, reset_less=True)
19 self.e_in = Signal((e_width, True), reset_less=True)
20 self.m_out = Signal(m_width, reset_less=True)
21 self.e_out = Signal((e_width, True), reset_less=True)
22
23 def elaborate(self, platform):
24 m = Module()
25
26 espec = (self.e_width, True)
27 mwid = self.m_width
28
29 msr = MultiShiftRMerge(mwid, espec)
30 m.submodules.multishift_r = msr
31
32 m.d.comb += [
33 # connect multi-shifter to inp/out mantissa (and ediff)
34 msr.inp.eq(self.m_in),
35 msr.diff.eq(self.ediff),
36 self.m_out.eq(msr.m),
37 self.e_out.eq(self.e_in + self.ediff),
38 ]
39
40
41 return m
42
43