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[ieee754fpu.git] / src / ieee754 / fpcommon / getop.py
1 # IEEE Floating Point Adder (Single Precision)
2 # Copyright (C) Jonathan P Dawson 2013
3 # 2013-12-12
4
5 from nmigen import Module, Signal, Elaboratable
6 from nmigen.lib.coding import PriorityEncoder
7 from nmigen.cli import main, verilog
8 from math import log
9
10 from ieee754.fpcommon.fpbase import FPOpIn, FPBase, FPNumBase
11 from nmutil.singlepipe import PrevControl
12 from nmutil.concurrentunit import PipeContext as FPPipeContext
13
14 from nmutil import nmoperator
15
16
17 class FPGetOpMod(Elaboratable):
18 def __init__(self, width):
19 self.in_op = FPOpIn(width)
20 self.in_op.data_i = Signal(width)
21 self.out_op = Signal(width)
22 self.out_decode = Signal(reset_less=True)
23
24 def elaborate(self, platform):
25 m = Module()
26 m.d.comb += self.out_decode.eq((self.in_op.ready_o) & \
27 (self.in_op.valid_i_test))
28 m.submodules.get_op_in = self.in_op
29 with m.If(self.out_decode):
30 m.d.comb += [
31 self.out_op.eq(self.in_op.v),
32 ]
33 return m
34
35
36 class FPNumBase2Ops:
37
38 def __init__(self, width, id_wid, m_extra=True):
39 self.a = FPNumBase(width, m_extra)
40 self.b = FPNumBase(width, m_extra)
41 self.muxid = Signal(id_wid, reset_less=True)
42
43 def eq(self, i):
44 return [self.a.eq(i.a), self.b.eq(i.b), self.muxid.eq(i.muxid)]
45
46 def ports(self):
47 return [self.a, self.b, self.muxid]
48
49
50 class FPGet2OpMod(PrevControl):
51 def __init__(self, width, id_wid, op_wid=None):
52 PrevControl.__init__(self)
53 self.width = width
54 self.id_wid = id_wid
55 self.data_i = self.ispec()
56 self.i = self.data_i
57 self.o = self.ospec()
58
59 def ispec(self):
60 return FPBaseData(self.width, self.id_wid, self.op_wid)
61
62 def ospec(self):
63 return FPBaseData(self.width, self.id_wid, self.op_wid)
64
65 def process(self, i):
66 return self.o
67
68 def elaborate(self, platform):
69 m = PrevControl.elaborate(self, platform)
70 with m.If(self.trigger):
71 m.d.comb += [
72 self.o.eq(self.data_i),
73 ]
74 return m
75
76