1 # IEEE Floating Point Adder (Single Precision)
2 # Copyright (C) Jonathan P Dawson 2013
5 from nmigen
import Module
, Signal
, Elaboratable
6 from nmigen
.cli
import main
, verilog
8 from ieee754
.fpcommon
.fpbase
import FPNumBase
, FPNumBaseRecord
9 from ieee754
.fpcommon
.fpbase
import FPState
10 from .postnormalise
import FPNorm1Data
15 def __init__(self
, width
, id_wid
):
16 self
.z
= FPNumBaseRecord(width
, False)
17 self
.mid
= Signal(id_wid
, reset_less
=True) # multiplex ID
18 # pipeline bypass [data comes from specialcases]
19 self
.out_do_z
= Signal(reset_less
=True)
20 self
.oz
= Signal(width
, reset_less
=True)
23 return [self
.z
.eq(i
.z
), self
.out_do_z
.eq(i
.out_do_z
), self
.oz
.eq(i
.oz
),
27 class FPRoundMod(Elaboratable
):
29 def __init__(self
, width
, id_wid
):
33 self
.out_z
= self
.ospec()
36 return FPNorm1Data(self
.width
, self
.id_wid
)
39 return FPRoundData(self
.width
, self
.id_wid
)
44 def setup(self
, m
, i
):
45 m
.submodules
.roundz
= self
46 m
.d
.comb
+= self
.i
.eq(i
)
48 def elaborate(self
, platform
):
50 m
.d
.comb
+= self
.out_z
.eq(self
.i
) # copies mid, z, out_do_z
51 with m
.If(~self
.i
.out_do_z
): # bypass wasn't enabled
52 with m
.If(self
.i
.roundz
):
53 m
.d
.comb
+= self
.out_z
.z
.m
.eq(self
.i
.z
.m
+ 1) # mantissa up
54 with m
.If(self
.i
.z
.m
== self
.i
.z
.m1s
): # all 1s
55 m
.d
.comb
+= self
.out_z
.z
.e
.eq(self
.i
.z
.e
+ 1) # exponent up
60 class FPRound(FPState
):
62 def __init__(self
, width
, id_wid
):
63 FPState
.__init
__(self
, "round")
64 self
.mod
= FPRoundMod(width
)
65 self
.out_z
= self
.ospec()
68 return self
.mod
.ispec()
71 return self
.mod
.ospec()
73 def setup(self
, m
, i
):
74 """ links module to inputs and outputs
79 m
.d
.sync
+= self
.out_z
.eq(self
.mod
.out_z
)
80 m
.d
.sync
+= self
.out_z
.mid
.eq(self
.mod
.o
.mid
)
83 m
.next
= "corrections"