src/ieee754/fpcommon/roundz.py

   1 # IEEE Floating Point Adder (Single Precision)
   2 # Copyright (C) Jonathan P Dawson 2013
   3 # 2013-12-12
   4
   5 from nmigen import Module, Signal
   6 from nmigen.cli import main, verilog
   7
   8 from nmutil.pipemodbase import FPModBase
   9 from ieee754.fpcommon.fpbase import FPNumBase, FPNumBaseRecord
  10 from ieee754.fpcommon.getop import FPPipeContext
  11 from ieee754.fpcommon.postnormalise import FPNorm1Data
  12
  13
  14 class FPRoundData:
  15
  16     def __init__(self, pspec):
  17         width = pspec.width
  18         self.z = FPNumBaseRecord(width, False, name="z")
  19         self.ctx = FPPipeContext(pspec)
  20         self.muxid = self.ctx.muxid
  21         # pipeline bypass [data comes from specialcases]
  22         self.out_do_z = Signal(reset_less=True)
  23         self.oz = Signal(width, reset_less=True)
  24
  25     def eq(self, i):
  26         ret = [self.z.eq(i.z), self.out_do_z.eq(i.out_do_z), self.oz.eq(i.oz),
  27                self.ctx.eq(i.ctx)]
  28         return ret
  29
  30
  31 class FPRoundMod(FPModBase):
  32
  33     def __init__(self, pspec):
  34         super().__init__(pspec, "roundz")
  35
  36     def ispec(self):
  37         return FPNorm1Data(self.pspec)
  38
  39     def ospec(self):
  40         return FPRoundData(self.pspec)
  41
  42     def elaborate(self, platform):
  43         m = Module()
  44         comb = m.d.comb
  45
  46         comb += self.o.eq(self.i)  # copies muxid, z, out_do_z
  47         with m.If(~self.i.out_do_z):  # bypass wasn't enabled
  48             with m.If(self.i.roundz):
  49                 comb += self.o.z.m.eq(self.i.z.m + 1)  # mantissa up
  50                 with m.If(self.i.z.m == self.i.z.m1s):  # all 1s
  51                     # exponent up
  52                     comb += self.o.z.e.eq(self.i.z.e + 1)
  53
  54         return m