add FPSCR with parts
[ieee754fpu.git] / src / ieee754 / fpcommon / test / test_fpscr.py
1 import unittest
2 from nmigen import Shape
3 from ieee754.fpcommon.fpscr import FPSCR, RoundingMode
4
5
6 class TestFPSCR(unittest.TestCase):
7 def test_FPSCR_layout(self):
8 expected = (
9 ('RN', RoundingMode),
10 ('NI', 1),
11 ('XE', 1),
12 ('ZE', 1),
13 ('UE', 1),
14 ('OE', 1),
15 ('VE', 1),
16 ('VXCVI', 1),
17 ('VXSQRT', 1),
18 ('VXSOFT', 1),
19 ('rsvd1', 1),
20 ('FPRF', (
21 ('FPCC', (
22 ('FU', 1),
23 ('FE', 1),
24 ('FG', 1),
25 ('FL', 1))),
26 ('C', 1))),
27 ('FI', 1),
28 ('FR', 1),
29 ('VXVC', 1),
30 ('VXIMZ', 1),
31 ('VXZDZ', 1),
32 ('VXIDI', 1),
33 ('VXISI', 1),
34 ('VXSNAN', 1),
35 ('XX', 1),
36 ('ZX', 1),
37 ('UX', 1),
38 ('OX', 1),
39 ('VX', 1),
40 ('FEX', 1),
41 ('FX', 1),
42 ('DRN', 3),
43 ('rsvd2', 29))
44 self.assertEqual(FPSCR.layout, expected)
45
46 def test_FPSCR_against_openpower_isa(self):
47 try:
48 from openpower.fpscr import FPSCRRecord
49 except ImportError:
50 self.skipTest("openpower-isa not installed")
51 expected = dict(FPSCRRecord.layout)
52 self.assertEqual(expected['RN'], Shape.cast(RoundingMode).width)
53 expected['RN'] = RoundingMode
54 expected = repr(expected).replace("[", "(").replace("]", ")")
55 self.assertEqual(repr(dict(FPSCR.layout)), expected)
56
57 def test_parts_are_complete_without_overlaps(self):
58 fields = {}
59 for part in FPSCR.Part:
60 if part is FPSCR.PART:
61 continue
62 for name, ty in part.layout:
63 self.assertNotIn(name, fields)
64 fields[name] = ty
65 self.assertEqual(fields, dict(FPSCR.layout))
66
67
68 if __name__ == '__main__':
69 unittest.main()