src/ieee754/fpdiv/div0.py

   1 """IEEE754 Floating Point Divider
   2
   3 Relevant bugreport: http://bugs.libre-riscv.org/show_bug.cgi?id=99
   4 """
   5
   6 from nmigen import Module, Signal, Cat, Elaboratable
   7 from nmigen.cli import main, verilog
   8
   9 from ieee754.fpcommon.fpbase import FPNumBaseRecord
  10 from ieee754.fpcommon.fpbase import FPState
  11 from ieee754.fpcommon.denorm import FPSCData
  12
  13
  14 class FPDivStage0Data:
  15
  16     def __init__(self, width, id_wid):
  17         self.z = FPNumBaseRecord(width, False)
  18         self.out_do_z = Signal(reset_less=True)
  19         self.oz = Signal(width, reset_less=True)
  20
  21         # TODO: here is where Q and R would be put, and passed
  22         # down to Stage1 processing.
  23
  24         mw = (self.z.m_width)*2 - 1 + 3 # sticky/round/guard bits + (2*mant) - 1
  25         self.product = Signal(mw, reset_less=True)
  26
  27         self.mid = Signal(id_wid, reset_less=True)
  28
  29     def eq(self, i):
  30         return [self.z.eq(i.z), self.out_do_z.eq(i.out_do_z), self.oz.eq(i.oz),
  31                 self.product.eq(i.product), self.mid.eq(i.mid)]
  32
  33
  34 class FPDivStage0Mod(Elaboratable):
  35
  36     def __init__(self, width, id_wid):
  37         self.width = width
  38         self.id_wid = id_wid
  39         self.i = self.ispec()
  40         self.o = self.ospec()
  41
  42     def ispec(self):
  43         return FPSCData(self.width, self.id_wid, False)
  44
  45     def ospec(self):
  46         return FPDivStage0Data(self.width, self.id_wid)
  47
  48     def process(self, i):
  49         return self.o
  50
  51     def setup(self, m, i):
  52         """ links module to inputs and outputs
  53         """
  54         m.submodules.div0 = self
  55         m.d.comb += self.i.eq(i)
  56
  57     def elaborate(self, platform):
  58         m = Module()
  59
  60         # XXX TODO, actual DIV code here.  this class would be
  61         # "step one" which takes the pre-normalised data and
  62         # *begins* the processing phase (enters the massive DIV
  63         # pipeline chain)
  64
  65         # store intermediate tests (and zero-extended mantissas)
  66         am0 = Signal(len(self.i.a.m)+1, reset_less=True)
  67         bm0 = Signal(len(self.i.b.m)+1, reset_less=True)
  68         m.d.comb += [
  69                      am0.eq(Cat(self.i.a.m, 0)),
  70                      bm0.eq(Cat(self.i.b.m, 0))
  71                     ]
  72         # same-sign (both negative or both positive) div mantissas
  73         with m.If(~self.i.out_do_z):
  74             m.d.comb += [self.o.z.e.eq(self.i.a.e + self.i.b.e + 1),
  75                          # TODO: no, not product, first stage Q and R etc. etc.
  76                          # go here.
  77                          self.o.product.eq(am0 * bm0 * 4),
  78                          self.o.z.s.eq(self.i.a.s ^ self.i.b.s)
  79                 ]
  80
  81         m.d.comb += self.o.oz.eq(self.i.oz)
  82         m.d.comb += self.o.out_do_z.eq(self.i.out_do_z)
  83         m.d.comb += self.o.mid.eq(self.i.mid)
  84         return m
  85
  86
  87 class FPDivStage0(FPState):
  88     """ First stage of div.
  89     """
  90
  91     def __init__(self, width, id_wid):
  92         FPState.__init__(self, "divider_0")
  93         self.mod = FPDivStage0Mod(width)
  94         self.o = self.mod.ospec()
  95
  96     def setup(self, m, i):
  97         """ links module to inputs and outputs
  98         """
  99         self.mod.setup(m, i)
 100
 101         # NOTE: these could be done as combinatorial (merge div0+div1)
 102         m.d.sync += self.o.eq(self.mod.o)
 103
 104     def action(self, m):
 105         m.next = "divider_1"