src/ieee754/fpdiv/div0.py

   1 """IEEE754 Floating Point Divider
   2
   3 Relevant bugreport: http://bugs.libre-riscv.org/show_bug.cgi?id=99
   4 """
   5
   6 from nmigen import Module, Signal, Cat, Elaboratable
   7 from nmigen.cli import main, verilog
   8
   9 from ieee754.fpcommon.fpbase import (FPNumBaseRecord, Overflow)
  10 from ieee754.fpcommon.fpbase import FPState
  11 from ieee754.fpcommon.denorm import FPSCData
  12
  13
  14 class FPDivStage0Data:
  15
  16     def __init__(self, width, id_wid):
  17         self.z = FPNumBaseRecord(width, False)
  18         self.out_do_z = Signal(reset_less=True)
  19         self.oz = Signal(width, reset_less=True)
  20         self.of = Overflow()
  21
  22         # TODO: here is where Q and R would be put, and passed
  23         # down to Stage1 processing.
  24
  25         mw = (self.z.m_width)*2 - 1 + 3 # sticky/round/guard bits + (2*mant) - 1
  26         self.product = Signal(mw, reset_less=True)
  27
  28         self.mid = Signal(id_wid, reset_less=True)
  29
  30     def eq(self, i):
  31         return [self.z.eq(i.z), self.out_do_z.eq(i.out_do_z), self.oz.eq(i.oz),
  32                 self.of.eq(i.of),
  33                 self.product.eq(i.product), self.mid.eq(i.mid)]
  34
  35
  36 class FPDivStage0Mod(Elaboratable):
  37
  38     def __init__(self, width, id_wid):
  39         self.width = width
  40         self.id_wid = id_wid
  41         self.i = self.ispec()
  42         self.o = self.ospec()
  43
  44     def ispec(self):
  45         return FPSCData(self.width, self.id_wid, False)
  46
  47     def ospec(self):
  48         return FPDivStage0Data(self.width, self.id_wid)
  49
  50     def process(self, i):
  51         return self.o
  52
  53     def setup(self, m, i):
  54         """ links module to inputs and outputs
  55         """
  56         m.submodules.div0 = self
  57         m.d.comb += self.i.eq(i)
  58
  59     def elaborate(self, platform):
  60         m = Module()
  61
  62         # XXX TODO, actual DIV code here.  this class would be
  63         # "step one" which takes the pre-normalised data (see ispec) and
  64         # *begins* the processing phase (enters the massive DIV
  65         # pipeline chain) - see ospec.
  66
  67         # NOTE: this stage does *NOT* do *ACTUAL* DIV processing,
  68         # it is PURELY the *ENTRY* point into the chain, performing
  69         # "preparation" work
  70
  71         # store intermediate tests (and zero-extended mantissas)
  72         am0 = Signal(len(self.i.a.m)+1, reset_less=True)
  73         bm0 = Signal(len(self.i.b.m)+1, reset_less=True)
  74         m.d.comb += [
  75                      am0.eq(Cat(self.i.a.m, 0)),
  76                      bm0.eq(Cat(self.i.b.m, 0))
  77                     ]
  78         # same-sign (both negative or both positive) div mantissas
  79         with m.If(~self.i.out_do_z):
  80             m.d.comb += [self.o.z.e.eq(self.i.a.e + self.i.b.e + 1),
  81                          # TODO: no, not product, first stage Q and R etc. etc.
  82                          # go here.
  83                          self.o.product.eq(am0 * bm0 * 4),
  84                          self.o.z.s.eq(self.i.a.s ^ self.i.b.s)
  85                 ]
  86
  87         m.d.comb += self.o.oz.eq(self.i.oz)
  88         m.d.comb += self.o.out_do_z.eq(self.i.out_do_z)
  89         m.d.comb += self.o.mid.eq(self.i.mid)
  90         return m
  91
  92
  93 class FPDivStage0(FPState):
  94     """ First stage of div.
  95     """
  96
  97     def __init__(self, width, id_wid):
  98         FPState.__init__(self, "divider_0")
  99         self.mod = FPDivStage0Mod(width)
 100         self.o = self.mod.ospec()
 101
 102     def setup(self, m, i):
 103         """ links module to inputs and outputs
 104         """
 105         self.mod.setup(m, i)
 106
 107         # NOTE: these could be done as combinatorial (merge div0+div1)
 108         m.d.sync += self.o.eq(self.mod.o)
 109
 110     def action(self, m):
 111         m.next = "divider_1"