1 """IEEE754 Floating Point Divider
3 Relevant bugreport: http://bugs.libre-riscv.org/show_bug.cgi?id=99
6 from nmigen
import Module
, Signal
, Cat
, Elaboratable
7 from nmigen
.cli
import main
, verilog
9 from ieee754
.fpcommon
.fpbase
import (FPNumBaseRecord
, Overflow
)
10 from ieee754
.fpcommon
.fpbase
import FPState
11 from ieee754
.fpcommon
.denorm
import FPSCData
12 from ieee754
.fpcommon
.getop
import FPPipeContext
15 # TODO: delete (replace by DivPipeCoreInputData)
16 class FPDivStage0Data
:
18 def __init__(self
, width
, pspec
):
19 self
.z
= FPNumBaseRecord(width
, False)
20 self
.out_do_z
= Signal(reset_less
=True)
21 self
.oz
= Signal(width
, reset_less
=True)
23 self
.ctx
= FPPipeContext(width
, pspec
) # context: muxid, operator etc.
24 self
.muxid
= self
.ctx
.muxid
# annoying. complicated.
26 # TODO: here is where Q and R would be put, and passed
27 # down to Stage1 processing.
29 mw
= (self
.z
.m_width
)*2 - 1 + 3 # sticky/round/guard bits + (2*mant) - 1
30 self
.product
= Signal(mw
, reset_less
=True)
33 return [self
.z
.eq(i
.z
), self
.out_do_z
.eq(i
.out_do_z
), self
.oz
.eq(i
.oz
),
34 self
.product
.eq(i
.product
), self
.ctx
.eq(i
.ctx
)]
37 class FPDivStage0Mod(Elaboratable
):
39 def __init__(self
, width
, id_wid
):
46 return FPSCData(self
.width
, self
.id_wid
, False)
49 return FPDivStage0Data(self
.width
, self
.id_wid
)
54 def setup(self
, m
, i
):
55 """ links module to inputs and outputs
57 m
.submodules
.div0
= self
58 m
.d
.comb
+= self
.i
.eq(i
)
60 def elaborate(self
, platform
):
63 # XXX TODO, actual DIV code here. this class would be
64 # "step one" which takes the pre-normalised data (see ispec) and
65 # *begins* the processing phase (enters the massive DIV
66 # pipeline chain) - see ospec.
68 # NOTE: this stage does *NOT* do *ACTUAL* DIV processing,
69 # it is PURELY the *ENTRY* point into the chain, performing
72 # store intermediate tests (and zero-extended mantissas)
73 am0
= Signal(len(self
.i
.a
.m
)+1, reset_less
=True)
74 bm0
= Signal(len(self
.i
.b
.m
)+1, reset_less
=True)
76 am0
.eq(Cat(self
.i
.a
.m
, 0)),
77 bm0
.eq(Cat(self
.i
.b
.m
, 0))
79 # same-sign (both negative or both positive) div mantissas
80 with m
.If(~self
.i
.out_do_z
):
81 m
.d
.comb
+= [self
.o
.z
.e
.eq(self
.i
.a
.e
+ self
.i
.b
.e
+ 1),
82 # TODO: no, not product, first stage Q and R etc. etc.
84 self
.o
.product
.eq(am0
* bm0
* 4),
85 self
.o
.z
.s
.eq(self
.i
.a
.s ^ self
.i
.b
.s
)
88 m
.d
.comb
+= self
.o
.oz
.eq(self
.i
.oz
)
89 m
.d
.comb
+= self
.o
.out_do_z
.eq(self
.i
.out_do_z
)
90 m
.d
.comb
+= self
.o
.ctx
.eq(self
.i
.ctx
)
94 class FPDivStage0(FPState
):
95 """ First stage of div.
98 def __init__(self
, width
, id_wid
):
99 FPState
.__init
__(self
, "divider_0")
100 self
.mod
= FPDivStage0Mod(width
)
101 self
.o
= self
.mod
.ospec()
103 def setup(self
, m
, i
):
104 """ links module to inputs and outputs
108 # NOTE: these could be done as combinatorial (merge div0+div1)
109 m
.d
.sync
+= self
.o
.eq(self
.mod
.o
)