src/ieee754/fpdiv/div0.py

   1 """IEEE754 Floating Point Divider
   2
   3 Relevant bugreport: http://bugs.libre-riscv.org/show_bug.cgi?id=99
   4 """
   5
   6 from nmigen import Module, Signal, Cat, Elaboratable
   7 from nmigen.cli import main, verilog
   8
   9 from ieee754.fpcommon.fpbase import (FPNumBaseRecord, Overflow)
  10 from ieee754.fpcommon.fpbase import FPState
  11 from ieee754.fpcommon.denorm import FPSCData
  12 from ieee754.fpcommon.getop import FPPipeContext
  13
  14
  15 # TODO: delete (replace by DivPipeCoreInputData)
  16 class FPDivStage0Data:
  17
  18     def __init__(self, width, pspec):
  19         self.z = FPNumBaseRecord(width, False)
  20         self.out_do_z = Signal(reset_less=True)
  21         self.oz = Signal(width, reset_less=True)
  22         self.of = Overflow()
  23
  24         self.ctx = FPPipeContext(width, pspec) # context: muxid, operator etc.
  25         self.muxid = self.ctx.muxid             # annoying. complicated.
  26
  27         # TODO: here is where Q and R would be put, and passed
  28         # down to Stage1 processing.
  29
  30         mw = (self.z.m_width)*2 - 1 + 3 # sticky/round/guard bits + (2*mant) - 1
  31         self.product = Signal(mw, reset_less=True)
  32
  33     def eq(self, i):
  34         return [self.z.eq(i.z), self.out_do_z.eq(i.out_do_z), self.oz.eq(i.oz),
  35                 self.of.eq(i.of),
  36                 self.product.eq(i.product), self.ctx.eq(i.ctx)]
  37
  38
  39 class FPDivStage0Mod(Elaboratable):
  40
  41     def __init__(self, width, id_wid):
  42         self.width = width
  43         self.id_wid = id_wid
  44         self.i = self.ispec()
  45         self.o = self.ospec()
  46
  47     def ispec(self):
  48         return FPSCData(self.width, self.id_wid, False)
  49
  50     def ospec(self):
  51         return FPDivStage0Data(self.width, self.id_wid)
  52
  53     def process(self, i):
  54         return self.o
  55
  56     def setup(self, m, i):
  57         """ links module to inputs and outputs
  58         """
  59         m.submodules.div0 = self
  60         m.d.comb += self.i.eq(i)
  61
  62     def elaborate(self, platform):
  63         m = Module()
  64
  65         # XXX TODO, actual DIV code here.  this class would be
  66         # "step one" which takes the pre-normalised data (see ispec) and
  67         # *begins* the processing phase (enters the massive DIV
  68         # pipeline chain) - see ospec.
  69
  70         # NOTE: this stage does *NOT* do *ACTUAL* DIV processing,
  71         # it is PURELY the *ENTRY* point into the chain, performing
  72         # "preparation" work
  73
  74         # store intermediate tests (and zero-extended mantissas)
  75         am0 = Signal(len(self.i.a.m)+1, reset_less=True)
  76         bm0 = Signal(len(self.i.b.m)+1, reset_less=True)
  77         m.d.comb += [
  78                      am0.eq(Cat(self.i.a.m, 0)),
  79                      bm0.eq(Cat(self.i.b.m, 0))
  80                     ]
  81         # same-sign (both negative or both positive) div mantissas
  82         with m.If(~self.i.out_do_z):
  83             m.d.comb += [self.o.z.e.eq(self.i.a.e + self.i.b.e + 1),
  84                          # TODO: no, not product, first stage Q and R etc. etc.
  85                          # go here.
  86                          self.o.product.eq(am0 * bm0 * 4),
  87                          self.o.z.s.eq(self.i.a.s ^ self.i.b.s)
  88                 ]
  89
  90         m.d.comb += self.o.oz.eq(self.i.oz)
  91         m.d.comb += self.o.out_do_z.eq(self.i.out_do_z)
  92         m.d.comb += self.o.ctx.eq(self.i.ctx)
  93         return m
  94
  95
  96 class FPDivStage0(FPState):
  97     """ First stage of div.
  98     """
  99
 100     def __init__(self, width, id_wid):
 101         FPState.__init__(self, "divider_0")
 102         self.mod = FPDivStage0Mod(width)
 103         self.o = self.mod.ospec()
 104
 105     def setup(self, m, i):
 106         """ links module to inputs and outputs
 107         """
 108         self.mod.setup(m, i)
 109
 110         # NOTE: these could be done as combinatorial (merge div0+div1)
 111         m.d.sync += self.o.eq(self.mod.o)
 112
 113     def action(self, m):
 114         m.next = "divider_1"