add bug cross-reference to #113 for FCVT unit tests
[ieee754fpu.git] / src / ieee754 / fpdiv / pipeline.py
1 """IEEE Floating Point Divider Pipeline
2
3 Relevant bugreport: http://bugs.libre-riscv.org/show_bug.cgi?id=99
4
5 Stack looks like this:
6
7 scnorm - FPDIVSpecialCasesDeNorm ispec FPADDBaseData
8 ------ ospec FPSCData
9
10 StageChain: FPDIVSpecialCasesMod,
11 FPAddDeNormMod
12
13 pipediv0 - FPDivStagesSetup ispec FPSCData
14 -------- ospec DivPipeCoreInterstageData
15
16 StageChain: FPDivStage0Mod,
17 DivPipeSetupStage,
18 DivPipeCalculateStage,
19 ...
20 DivPipeCalculateStage
21
22 pipediv1 - FPDivStagesIntermediate ispec DivPipeCoreInterstageData
23 -------- ospec DivPipeCoreInterstageData
24
25 StageChain: DivPipeCalculateStage,
26 ...
27 DivPipeCalculateStage
28 ...
29 ...
30
31 pipediv5 - FPDivStageFinal ispec FPDivStage0Data
32 -------- ospec FPAddStage1Data
33
34 StageChain: DivPipeCalculateStage,
35 ...
36 DivPipeCalculateStage,
37 DivPipeFinalStage,
38 FPDivStage2Mod
39
40 normpack - FPNormToPack ispec FPAddStage1Data
41 -------- ospec FPPackData
42
43 StageChain: Norm1ModSingle,
44 RoundMod,
45 CorrectionsMod,
46 PackMod
47
48 the number of combinatorial StageChains (n_comb_stages) in
49 FPDivStages is an argument arranged to get the length of the whole
50 pipeline down to sane numbers.
51
52 the reason for keeping the number of stages down is that for every
53 pipeline clock delay, a corresponding ReservationStation is needed.
54 if there are 24 pipeline stages, we need a whopping TWENTY FOUR
55 RS's. that's far too many. 6 is just about an acceptable number.
56 even 8 is starting to get alarmingly high.
57 """
58
59 from nmigen import Module
60 from nmigen.cli import main, verilog
61
62 from nmutil.singlepipe import ControlBase
63 from nmutil.concurrentunit import ReservationStations, num_bits
64
65 from ieee754.fpcommon.getop import FPADDBaseData
66 from ieee754.fpcommon.denorm import FPSCData
67 from ieee754.fpcommon.pack import FPPackData
68 from ieee754.fpcommon.normtopack import FPNormToPack
69 from ieee754.fpdiv.specialcases import FPDIVSpecialCasesDeNorm
70 from ieee754.fpdiv.divstages import (FPDivStagesSetup,
71 FPDivStagesIntermediate,
72 FPDivStagesFinal)
73 from ieee754.pipeline import PipelineSpec
74
75
76 class FPDIVBasePipe(ControlBase):
77 def __init__(self, pspec):
78 ControlBase.__init__(self)
79 self.pspec = pspec
80
81 def elaborate(self, platform):
82 m = ControlBase.elaborate(self, platform)
83
84 pipechain = []
85 n_stages = 6 # TODO (depends on width)
86 n_comb_stages = 3 # TODO (depends on how many RS's we want)
87 # to which the answer: "as few as possible"
88 # is required. too many ReservationStations
89 # means "big problems".
90
91 for i in range(n_stages):
92
93 # needs to convert input from pipestart ospec
94 if i == 0:
95 kls = FPDivStagesSetup
96 n_comb_stages -= 1 # reduce due to work done at start
97
98 # needs to convert output to pipeend ispec
99 elif i == n_stages - 1:
100 kls = FPDivStagesFinal
101 n_comb_stages -= 1 # FIXME - reduce due to work done at end?
102
103 # intermediary stage
104 else:
105 kls = FPDivStagesIntermediate
106
107 pipechain.append(kls(self.pspec, n_comb_stages))
108
109 # start and end: unpack/specialcases then normalisation/packing
110 pipestart = FPDIVSpecialCasesDeNorm(self.pspec)
111 pipeend = FPNormToPack(self.pspec)
112
113 # add submodules
114 m.submodules.scnorm = pipestart
115 for i, p in enumerate(pipechain):
116 setattr(m.submodules, "pipediv%d" % i, p)
117 m.submodules.normpack = pipeend
118
119 # ControlBase.connect creates the "eqs" needed to connect each pipe
120 m.d.comb += self.connect([pipestart] + pipechain + [pipeend])
121
122 return m
123
124
125 class FPDIVMuxInOut(ReservationStations):
126 """ Reservation-Station version of FPDIV pipeline.
127
128 * fan-in on inputs (an array of FPADDBaseData: a,b,mid)
129 * N-stage divider pipeline
130 * fan-out on outputs (an array of FPPackData: z,mid)
131
132 Fan-in and Fan-out are combinatorial.
133
134 :op_wid: - set this to the width of an operator which can
135 then be used to change the behaviour of the pipeline.
136 """
137
138 def __init__(self, width, num_rows, op_wid=0):
139 self.id_wid = num_bits(width)
140 self.pspec = PipelineSpec(width, self.id_wid, op_wid)
141 # XXX TODO - a class (or function?) that takes the pspec (right here)
142 # and creates... "something". that "something" MUST have an eq function
143 # new_pspec = deepcopy(self.pspec)
144 # new_pspec.opkls = DivPipeCoreOperation
145 # self.alu = FPDIVBasePipe(new_pspec)
146 self.alu = FPDIVBasePipe(self.pspec)
147 ReservationStations.__init__(self, num_rows)
148
149 def i_specfn(self):
150 return FPADDBaseData(self.pspec)
151
152 def o_specfn(self):
153 return FPPackData(self.pspec)