add cookie-cut fpdiv pipeline.py
[ieee754fpu.git] / src / ieee754 / fpdiv / pipeline.py
1 # IEEE Floating Point Adder (Single Precision)
2 # Copyright (C) Jonathan P Dawson 2013
3 # 2013-12-12
4
5 from nmigen import Module
6 from nmigen.cli import main, verilog
7
8 from nmutil.singlepipe import ControlBase
9 from nmutil.concurrentunit import ReservationStations, num_bits
10
11 from ieee754.fpcommon.getop import FPADDBaseData
12 from ieee754.fpcommon.denorm import FPSCData
13 from ieee754.fpcommon.pack import FPPackData
14 from ieee754.fpcommon.normtopack import FPNormToPack
15 from .specialcases import FPDivSpecialCasesDeNorm
16 from .mulstages import FPDivStages
17
18
19
20 class FPDIVBasePipe(ControlBase):
21 def __init__(self, width, id_wid):
22 ControlBase.__init__(self)
23 self.pipe1 = FPDivSpecialCasesDeNorm(width, id_wid)
24 self.pipe2 = FPDivStages(width, id_wid)
25 self.pipe3 = FPNormToPack(width, id_wid)
26
27 self._eqs = self.connect([self.pipe1, self.pipe2, self.pipe3])
28
29 def elaborate(self, platform):
30 m = ControlBase.elaborate(self, platform)
31 m.submodules.scnorm = self.pipe1
32 m.submodules.mulstages = self.pipe2
33 m.submodules.normpack = self.pipe3
34 m.d.comb += self._eqs
35 return m
36
37
38 class FPDIVMuxInOut(ReservationStations):
39 """ Reservation-Station version of FPDIV pipeline.
40
41 * fan-in on inputs (an array of FPADDBaseData: a,b,mid)
42 * 2-stage multiplier pipeline
43 * fan-out on outputs (an array of FPPackData: z,mid)
44
45 Fan-in and Fan-out are combinatorial.
46 """
47 def __init__(self, width, num_rows):
48 self.width = width
49 self.id_wid = num_bits(width)
50 self.alu = FPDIVBasePipe(width, self.id_wid)
51 ReservationStations.__init__(self, num_rows)
52
53 def i_specfn(self):
54 return FPADDBaseData(self.width, self.id_wid)
55
56 def o_specfn(self):
57 return FPPackData(self.width, self.id_wid)