src/ieee754/fpmul/mul0.py

   1 """IEEE754 Floating Point Multiplier Pipeline
   2
   3 Copyright (C) 2019 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
   4
   5 """
   6
   7 from nmigen import Module, Signal, Cat
   8 from nmigen.cli import main, verilog
   9
  10 from nmutil.pipemodbase import PipeModBase
  11 from ieee754.fpcommon.fpbase import FPNumBaseRecord
  12 from ieee754.fpcommon.denorm import FPSCData
  13 from ieee754.fpcommon.getop import FPPipeContext
  14 from ieee754.fpmul.datastructs import FPMulStage0Data
  15
  16
  17 class FPMulStage0Mod(PipeModBase):
  18
  19     def __init__(self, pspec):
  20         super().__init__(pspec, "mul0")
  21
  22     def ispec(self):
  23         return FPSCData(self.pspec, False)
  24
  25     def ospec(self):
  26         return FPMulStage0Data(self.pspec)
  27
  28     def elaborate(self, platform):
  29         m = Module()
  30         comb = m.d.comb
  31
  32         # store intermediate tests (and zero-extended mantissas)
  33         am0 = Signal(len(self.i.a.m)+1, reset_less=True)
  34         bm0 = Signal(len(self.i.b.m)+1, reset_less=True)
  35         comb += [ am0.eq(Cat(self.i.a.m, 0)),
  36                      bm0.eq(Cat(self.i.b.m, 0))
  37                 ]
  38         # same-sign (both negative or both positive) mul mantissas
  39         comb += [self.o.z.e.eq(self.i.a.e + self.i.b.e + 1),
  40                      self.o.product.eq(am0 * bm0 * 4),
  41                      self.o.z.s.eq(self.i.a.s ^ self.i.b.s)
  42         ]
  43
  44         # pass through context
  45         comb += self.o.oz.eq(self.i.oz)
  46         comb += self.o.out_do_z.eq(self.i.out_do_z)
  47         comb += self.o.ctx.eq(self.i.ctx)
  48
  49         return m