src/ieee754/fpmul/mul1.py

   1 # IEEE Floating Point Multiplier
   2
   3 from nmigen import Module, Signal, Elaboratable
   4 from nmigen.cli import main, verilog
   5
   6 from ieee754.fpcommon.fpbase import FPState
   7 from ieee754.fpcommon.postcalc import FPAddStage1Data
   8 from .mul0 import FPMulStage0Data
   9
  10
  11 class FPMulStage1Mod(FPState, Elaboratable):
  12     """ Second stage of mul: preparation for normalisation.
  13     """
  14
  15     def __init__(self, pspec):
  16         self.pspec = pspec
  17         self.i = self.ispec()
  18         self.o = self.ospec()
  19
  20     def ispec(self):
  21         return FPMulStage0Data(self.pspec)
  22
  23     def ospec(self):
  24         return FPAddStage1Data(self.pspec)
  25
  26     def process(self, i):
  27         return self.o
  28
  29     def setup(self, m, i):
  30         """ links module to inputs and outputs
  31         """
  32         m.submodules.mul1 = self
  33         #m.submodules.mul1_out_overflow = self.o.of
  34
  35         m.d.comb += self.i.eq(i)
  36
  37     def elaborate(self, platform):
  38         m = Module()
  39         m.d.comb += self.o.z.eq(self.i.z)
  40         with m.If(~self.i.out_do_z):
  41             p = Signal(len(self.i.product), reset_less=True)
  42             with m.If(self.i.product[-1]):
  43                 m.d.comb += p.eq(self.i.product)
  44             with m.Else():
  45                 # get 1 bit of extra accuracy if the mantissa top bit is zero
  46                 m.d.comb += p.eq(self.i.product<<1)
  47                 m.d.comb += self.o.z.e.eq(self.i.z.e-1)
  48             mw = self.o.z.m_width
  49             m.d.comb += [
  50                 self.o.z.m.eq(p[mw+2:]),
  51                 self.o.of.m0.eq(p[mw+2]),
  52                 self.o.of.guard.eq(p[mw+1]),
  53                 self.o.of.round_bit.eq(p[mw]),
  54                 self.o.of.sticky.eq(p[0:mw].bool())
  55             ]
  56
  57         m.d.comb += self.o.out_do_z.eq(self.i.out_do_z)
  58         m.d.comb += self.o.oz.eq(self.i.oz)
  59         m.d.comb += self.o.ctx.eq(self.i.ctx)
  60
  61         return m
  62
  63
  64 class FPMulStage1(FPState):
  65
  66     def __init__(self, pspec):
  67         FPState.__init__(self, "multiply_1")
  68         width = pspec.width
  69         self.mod = FPMulStage1Mod(pspec)
  70         self.out_z = FPNumBaseRecord(width, False)
  71         self.norm_stb = Signal()
  72
  73     def setup(self, m, i):
  74         """ links module to inputs and outputs
  75         """
  76         self.mod.setup(m, i)
  77
  78         m.d.sync += self.norm_stb.eq(0) # sets to zero when not in mul1 state
  79
  80         m.d.sync += self.out_z.eq(self.mod.out_z)
  81         m.d.sync += self.norm_stb.eq(1)
  82
  83     def action(self, m):
  84         m.next = "normalise_1"
  85