2 # SPDX-License-Identifier: LGPL-2.1-or-later
3 # See Notices.txt for copyright information
5 from nmigen
import Signal
, Module
, Elaboratable
6 from nmigen
.back
.pysim
import Simulator
, Delay
, Tick
, Passive
7 from nmigen
.cli
import verilog
, rtlil
9 from ieee754
.part
.partsig
import PartitionedSignal
13 def create_ilang(dut
, traces
, test_name
):
14 vl
= rtlil
.convert(dut
, ports
=traces
)
15 with
open("%s.il" % test_name
, "w") as f
:
19 def create_simulator(module
, traces
, test_name
):
20 create_ilang(module
, traces
, test_name
)
21 return Simulator(module
,
22 vcd_file
=open(test_name
+ ".vcd", "w"),
23 gtkw_file
=open(test_name
+ ".gtkw", "w"),
26 class TestAddMod(Elaboratable
):
27 def __init__(self
, width
, partpoints
):
28 self
.a
= PartitionedSignal(partpoints
, width
)
29 self
.b
= PartitionedSignal(partpoints
, width
)
30 self
.add_output
= Signal(width
)
31 self
.eq_output
= Signal(len(partpoints
))
33 def elaborate(self
, platform
):
37 m
.d
.comb
+= self
.eq_output
.eq(self
.a
== self
.b
)
38 m
.d
.comb
+= self
.add_output
.eq(self
.a
+ self
.b
)
43 class TestPartitionPoints(unittest
.TestCase
):
46 part_mask
= Signal(4) # divide into 4-bits
47 module
= TestAddMod(width
, part_mask
)
49 sim
= create_simulator(module
,
57 def test_add(msg_prefix
, *mask_list
):
58 for a
, b
in [(0x0000, 0x0000),
69 for mask
in mask_list
:
70 y |
= mask
& ((a
& mask
) + (b
& mask
))
71 outval
= (yield module
.add_output
)
72 msg
= f
"{msg_prefix}: 0x{a:X} + 0x{b:X}" + \
73 f
" => 0x{y:X} != 0x{outval:X}"
74 self
.assertEqual(y
, outval
, msg
)
76 yield from test_add("16-bit", 0xFFFF)
77 yield part_mask
.eq(0b10)
78 yield from test_add("8-bit", 0xFF00, 0x00FF)
79 yield part_mask
.eq(0b1111)
80 yield from test_add("4-bit", 0xF000, 0x0F00, 0x00F0, 0x000F)
82 def test_eq(msg_prefix
, *mask_list
):
83 for a
, b
in [(0x0000, 0x0000),
94 for i
, mask
in enumerate(mask_list
):
95 y |
= ((a
& mask
) == (b
& mask
)) << i
96 outval
= (yield module
.eq_output
)
97 msg
= f
"{msg_prefix}: 0x{a:X} + 0x{b:X}" + \
98 f
" => 0x{y:X} != 0x{outval:X}"
99 self
.assertEqual(y
, outval
, msg
)
100 yield part_mask
.eq(0)
101 yield from test_eq("16-bit", 0xFFFF)
102 yield part_mask
.eq(0b10)
103 yield from test_eq("8-bit", 0xFF00, 0x00FF)
104 yield part_mask
.eq(0b1111)
105 yield from test_eq("4-bit", 0xF000, 0x0F00, 0x00F0, 0x000F)
107 sim
.add_process(async_process
)
110 if __name__
== '__main__':