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[ieee754fpu.git] / src / ieee754 / part_cmp / reorder_results.py
1 # gt_combiner returns results that are in the wrong order from how
2 # they need to be. Specifically, if the partition gates are open, the
3 # bits need to be reversed through the width of the partition. This
4 # module does that
5 from nmigen import Signal, Module, Elaboratable, Mux
6
7
8 class ReorderResults(Elaboratable):
9 def __init__(self, width):
10 self.width = width
11 self.results_in = Signal(width, reset_less=True)
12 self.gates = Signal(width-1, reset_less=True)
13
14 self.output = Signal(width, reset_less=True)
15
16 def elaborate(self, platform):
17 m = Module()
18 comb = m.d.comb
19 width = self.width
20
21 current_result = self.results_in[-1]
22
23 for i in range(width-2, -1, -1): # counts down from width-1 to 0
24 cur = Signal()
25 comb += cur.eq(current_result)
26 comb += self.output[i+1].eq(cur)
27 current_result = Mux(self.gates[i], self.results_in[i], cur)
28
29 comb += self.output[0].eq(current_result)
30 return m