src/ieee754/part_mul_add/mul_pipe.py

   1 # SPDX-License-Identifier: LGPL-2.1-or-later
   2 # See Notices.txt for copyright information
   3 """Integer Multiplication."""
   4
   5 from nmigen import Signal, Module, Value, Elaboratable, Cat, C, Mux, Repl
   6 from nmigen.cli import main
   7
   8 from ieee754.part_mul_add.multiply import (InputData, OutputData,
   9                                            AllTerms, AddReduceInternal,
  10                                            Intermediates, FinalOut)
  11
  12 from nmutil.pipemodbase import PipeModBaseChain
  13 from nmutil.singlepipe import ControlBase
  14 from ieee754.pipeline import PipelineSpec
  15
  16
  17 class MulStages(PipeModBaseChain):
  18
  19     def __init__(self, pspec, part_pts):
  20         self.part_pts = part_pts
  21         super().__init__(pspec)
  22
  23     def get_chain(self):
  24         # chain AddReduce, Intermediates and FinalOut
  25         part_pts = self.part_pts
  26         n_inputs = 64 + 4
  27         at = AddReduceInternal(self.pspec, n_inputs, part_pts, partition_step=2)
  28         levels = at.levels
  29
  30         interm = Intermediates(self.pspec, part_pts)
  31         finalout = FinalOut(self.pspec, part_pts)
  32         self.output = finalout.o.output
  33
  34         return levels + [interm, finalout]
  35
  36
  37 class AllTermsPipe(PipeModBaseChain):
  38
  39     def __init__(self, pspec, n_inputs):
  40         self.n_inputs = n_inputs
  41         super().__init__(pspec)
  42
  43     def get_chain(self):
  44         """ gets module
  45         """
  46         nmod = AllTerms(self.pspec, self.n_inputs)
  47
  48         return [nmod]
  49
  50
  51 class MulPipe_8_16_32_64(ControlBase):
  52     """Signed/Unsigned 8/16/32/64-bit partitioned integer multiplier pipeline
  53     """
  54
  55     def __init__(self):
  56         """ register_levels: specifies the points in the cascade at which
  57             flip-flops are to be inserted.
  58         """
  59
  60         self.id_wid = 0 # num_bits(num_rows)
  61         self.op_wid = 0
  62         self.pspec = PipelineSpec(64, self.id_wid, self.op_wid, n_ops=3)
  63         self.pspec.n_parts = 8
  64
  65         ControlBase.__init__(self)
  66
  67         n_inputs = 64 + 4
  68         self.allterms = AllTermsPipe(self.pspec, n_inputs)
  69         stage = self.allterms.chain[0]
  70         part_pts = stage.i.part_pts
  71         self.mulstages = MulStages(self.pspec, part_pts)
  72
  73         self._eqs = self.connect([self.allterms, self.mulstages])
  74
  75         self.a = stage.i.a
  76         self.b = stage.i.b
  77         self.output = self.mulstages.output
  78
  79     def ispec(self):
  80         return InputData()
  81
  82     def ospec(self):
  83         return OutputData()
  84
  85     def elaborate(self, platform):
  86         m = ControlBase.elaborate(self, platform)
  87
  88         m.submodules.allterms = self.allterms
  89         m.submodules.mulstages = self.mulstages
  90         m.d.comb += self._eqs
  91
  92         return m
  93
  94
  95 if __name__ == "__main__":
  96     m = MulPipe_8_16_32_64()
  97     main(m, ports=[m.a,
  98                    m.b,
  99                    m.output,
 100                    ])