src/ieee754/part_mul_add/multiply.py

   1 # SPDX-License-Identifier: LGPL-2.1-or-later
   2 # See Notices.txt for copyright information
   3 """Integer Multiplication."""
   4
   5 from nmigen import Signal, Module, Value, Elaboratable, Cat, C, Mux, Repl
   6 from nmigen.hdl.ast import Assign
   7 from abc import ABCMeta, abstractmethod
   8 from nmigen.cli import main
   9
  10
  11 class PartitionPoints(dict):
  12     """Partition points and corresponding ``Value``s.
  13
  14     The points at where an ALU is partitioned along with ``Value``s that
  15     specify if the corresponding partition points are enabled.
  16
  17     For example: ``{1: True, 5: True, 10: True}`` with
  18     ``width == 16`` specifies that the ALU is split into 4 sections:
  19     * bits 0 <= ``i`` < 1
  20     * bits 1 <= ``i`` < 5
  21     * bits 5 <= ``i`` < 10
  22     * bits 10 <= ``i`` < 16
  23
  24     If the partition_points were instead ``{1: True, 5: a, 10: True}``
  25     where ``a`` is a 1-bit ``Signal``:
  26     * If ``a`` is asserted:
  27         * bits 0 <= ``i`` < 1
  28         * bits 1 <= ``i`` < 5
  29         * bits 5 <= ``i`` < 10
  30         * bits 10 <= ``i`` < 16
  31     * Otherwise
  32         * bits 0 <= ``i`` < 1
  33         * bits 1 <= ``i`` < 10
  34         * bits 10 <= ``i`` < 16
  35     """
  36
  37     def __init__(self, partition_points=None):
  38         """Create a new ``PartitionPoints``.
  39
  40         :param partition_points: the input partition points to values mapping.
  41         """
  42         super().__init__()
  43         if partition_points is not None:
  44             for point, enabled in partition_points.items():
  45                 if not isinstance(point, int):
  46                     raise TypeError("point must be a non-negative integer")
  47                 if point < 0:
  48                     raise ValueError("point must be a non-negative integer")
  49                 self[point] = Value.wrap(enabled)
  50
  51     def like(self, name=None, src_loc_at=0):
  52         """Create a new ``PartitionPoints`` with ``Signal``s for all values.
  53
  54         :param name: the base name for the new ``Signal``s.
  55         """
  56         if name is None:
  57             name = Signal(src_loc_at=1+src_loc_at).name  # get variable name
  58         retval = PartitionPoints()
  59         for point, enabled in self.items():
  60             retval[point] = Signal(enabled.shape(), name=f"{name}_{point}")
  61         return retval
  62
  63     def eq(self, rhs):
  64         """Assign ``PartitionPoints`` using ``Signal.eq``."""
  65         if set(self.keys()) != set(rhs.keys()):
  66             raise ValueError("incompatible point set")
  67         for point, enabled in self.items():
  68             yield enabled.eq(rhs[point])
  69
  70     def as_mask(self, width):
  71         """Create a bit-mask from `self`.
  72
  73         Each bit in the returned mask is clear only if the partition point at
  74         the same bit-index is enabled.
  75
  76         :param width: the bit width of the resulting mask
  77         """
  78         bits = []
  79         for i in range(width):
  80             if i in self:
  81                 bits.append(~self[i])
  82             else:
  83                 bits.append(True)
  84         return Cat(*bits)
  85
  86     def get_max_partition_count(self, width):
  87         """Get the maximum number of partitions.
  88
  89         Gets the number of partitions when all partition points are enabled.
  90         """
  91         retval = 1
  92         for point in self.keys():
  93             if point < width:
  94                 retval += 1
  95         return retval
  96
  97     def fits_in_width(self, width):
  98         """Check if all partition points are smaller than `width`."""
  99         for point in self.keys():
 100             if point >= width:
 101                 return False
 102         return True
 103
 104
 105 class FullAdder(Elaboratable):
 106     """Full Adder.
 107
 108     :attribute in0: the first input
 109     :attribute in1: the second input
 110     :attribute in2: the third input
 111     :attribute sum: the sum output
 112     :attribute carry: the carry output
 113     """
 114
 115     def __init__(self, width):
 116         """Create a ``FullAdder``.
 117
 118         :param width: the bit width of the input and output
 119         """
 120         self.in0 = Signal(width)
 121         self.in1 = Signal(width)
 122         self.in2 = Signal(width)
 123         self.sum = Signal(width)
 124         self.carry = Signal(width)
 125
 126     def elaborate(self, platform):
 127         """Elaborate this module."""
 128         m = Module()
 129         m.d.comb += self.sum.eq(self.in0 ^ self.in1 ^ self.in2)
 130         m.d.comb += self.carry.eq((self.in0 & self.in1)
 131                                   | (self.in1 & self.in2)
 132                                   | (self.in2 & self.in0))
 133         return m
 134
 135
 136 class PartitionedAdder(Elaboratable):
 137     """Partitioned Adder.
 138
 139     :attribute width: the bit width of the input and output. Read-only.
 140     :attribute a: the first input to the adder
 141     :attribute b: the second input to the adder
 142     :attribute output: the sum output
 143     :attribute partition_points: the input partition points. Modification not
 144         supported, except for by ``Signal.eq``.
 145     """
 146
 147     def __init__(self, width, partition_points):
 148         """Create a ``PartitionedAdder``.
 149
 150         :param width: the bit width of the input and output
 151         :param partition_points: the input partition points
 152         """
 153         self.width = width
 154         self.a = Signal(width)
 155         self.b = Signal(width)
 156         self.output = Signal(width)
 157         self.partition_points = PartitionPoints(partition_points)
 158         if not self.partition_points.fits_in_width(width):
 159             raise ValueError("partition_points doesn't fit in width")
 160         expanded_width = 0
 161         for i in range(self.width):
 162             if i in self.partition_points:
 163                 expanded_width += 1
 164             expanded_width += 1
 165         self._expanded_width = expanded_width
 166         self._expanded_a = Signal(expanded_width)
 167         self._expanded_b = Signal(expanded_width)
 168         self._expanded_output = Signal(expanded_width)
 169
 170     def elaborate(self, platform):
 171         """Elaborate this module."""
 172         m = Module()
 173         expanded_index = 0
 174         for i in range(self.width):
 175             if i in self.partition_points:
 176                 # add extra bit set to 0 + 0 for enabled partition points
 177                 # and 1 + 0 for disabled partition points
 178                 m.d.comb += self._expanded_a[expanded_index].eq(
 179                     ~self.partition_points[i])
 180                 m.d.comb += self._expanded_b[expanded_index].eq(0)
 181                 expanded_index += 1
 182             m.d.comb += self._expanded_a[expanded_index].eq(self.a[i])
 183             m.d.comb += self._expanded_b[expanded_index].eq(self.b[i])
 184             m.d.comb += self.output[i].eq(
 185                 self._expanded_output[expanded_index])
 186             expanded_index += 1
 187         # use only one addition to take advantage of look-ahead carry and
 188         # special hardware on FPGAs
 189         m.d.comb += self._expanded_output.eq(
 190             self._expanded_a + self._expanded_b)
 191         return m
 192
 193
 194 FULL_ADDER_INPUT_COUNT = 3
 195
 196
 197 class AddReduce(Elaboratable):
 198     """Add list of numbers together.
 199
 200     :attribute inputs: input ``Signal``s to be summed. Modification not
 201         supported, except for by ``Signal.eq``.
 202     :attribute register_levels: List of nesting levels that should have
 203         pipeline registers.
 204     :attribute output: output sum.
 205     :attribute partition_points: the input partition points. Modification not
 206         supported, except for by ``Signal.eq``.
 207     """
 208
 209     def __init__(self, inputs, output_width, register_levels, partition_points):
 210         """Create an ``AddReduce``.
 211
 212         :param inputs: input ``Signal``s to be summed.
 213         :param output_width: bit-width of ``output``.
 214         :param register_levels: List of nesting levels that should have
 215             pipeline registers.
 216         :param partition_points: the input partition points.
 217         """
 218         self.inputs = list(inputs)
 219         self._resized_inputs = [
 220             Signal(output_width, name=f"resized_inputs[{i}]")
 221             for i in range(len(self.inputs))]
 222         self.register_levels = list(register_levels)
 223         self.output = Signal(output_width)
 224         self.partition_points = PartitionPoints(partition_points)
 225         if not self.partition_points.fits_in_width(output_width):
 226             raise ValueError("partition_points doesn't fit in output_width")
 227         self._reg_partition_points = self.partition_points.like()
 228         max_level = AddReduce.get_max_level(len(self.inputs))
 229         for level in self.register_levels:
 230             if level > max_level:
 231                 raise ValueError(
 232                     "not enough adder levels for specified register levels")
 233
 234     @staticmethod
 235     def get_max_level(input_count):
 236         """Get the maximum level.
 237
 238         All ``register_levels`` must be less than or equal to the maximum
 239         level.
 240         """
 241         retval = 0
 242         while True:
 243             groups = AddReduce.full_adder_groups(input_count)
 244             if len(groups) == 0:
 245                 return retval
 246             input_count %= FULL_ADDER_INPUT_COUNT
 247             input_count += 2 * len(groups)
 248             retval += 1
 249
 250     def next_register_levels(self):
 251         """``Iterable`` of ``register_levels`` for next recursive level."""
 252         for level in self.register_levels:
 253             if level > 0:
 254                 yield level - 1
 255
 256     @staticmethod
 257     def full_adder_groups(input_count):
 258         """Get ``inputs`` indices for which a full adder should be built."""
 259         return range(0,
 260                      input_count - FULL_ADDER_INPUT_COUNT + 1,
 261                      FULL_ADDER_INPUT_COUNT)
 262
 263     def elaborate(self, platform):
 264         """Elaborate this module."""
 265         m = Module()
 266
 267         # resize inputs to correct bit-width and optionally add in
 268         # pipeline registers
 269         resized_input_assignments = [self._resized_inputs[i].eq(self.inputs[i])
 270                                      for i in range(len(self.inputs))]
 271         if 0 in self.register_levels:
 272             m.d.sync += resized_input_assignments
 273             m.d.sync += self._reg_partition_points.eq(self.partition_points)
 274         else:
 275             m.d.comb += resized_input_assignments
 276             m.d.comb += self._reg_partition_points.eq(self.partition_points)
 277
 278         groups = AddReduce.full_adder_groups(len(self.inputs))
 279         # if there are no full adders to create, then we handle the base cases
 280         # and return, otherwise we go on to the recursive case
 281         if len(groups) == 0:
 282             if len(self.inputs) == 0:
 283                 # use 0 as the default output value
 284                 m.d.comb += self.output.eq(0)
 285             elif len(self.inputs) == 1:
 286                 # handle single input
 287                 m.d.comb += self.output.eq(self._resized_inputs[0])
 288             else:
 289                 # base case for adding 2 or more inputs, which get recursively
 290                 # reduced to 2 inputs
 291                 assert len(self.inputs) == 2
 292                 adder = PartitionedAdder(len(self.output),
 293                                          self._reg_partition_points)
 294                 m.submodules.final_adder = adder
 295                 m.d.comb += adder.a.eq(self._resized_inputs[0])
 296                 m.d.comb += adder.b.eq(self._resized_inputs[1])
 297                 m.d.comb += self.output.eq(adder.output)
 298             return m
 299         # go on to handle recursive case
 300         intermediate_terms: List[Signal]
 301         intermediate_terms = []
 302
 303         def add_intermediate_term(value):
 304             intermediate_term = Signal(
 305                 len(self.output),
 306                 name=f"intermediate_terms[{len(intermediate_terms)}]")
 307             intermediate_terms.append(intermediate_term)
 308             m.d.comb += intermediate_term.eq(value)
 309
 310         part_mask = self._reg_partition_points.as_mask(len(self.output))
 311
 312         # create full adders for this recursive level.
 313         # this shrinks N terms to 2 * (N // 3) plus the remainder
 314         for i in groups:
 315             adder_i = FullAdder(len(self.output))
 316             setattr(m.submodules, f"adder_{i}", adder_i)
 317             m.d.comb += adder_i.in0.eq(self._resized_inputs[i])
 318             m.d.comb += adder_i.in1.eq(self._resized_inputs[i + 1])
 319             m.d.comb += adder_i.in2.eq(self._resized_inputs[i + 2])
 320             add_intermediate_term(adder_i.sum)
 321             shifted_carry = adder_i.carry << 1
 322             # mask out carry bits to prevent carries between partitions
 323             add_intermediate_term((adder_i.carry << 1) & part_mask)
 324         # handle the remaining inputs.
 325         if len(self.inputs) % FULL_ADDER_INPUT_COUNT == 1:
 326             add_intermediate_term(self._resized_inputs[-1])
 327         elif len(self.inputs) % FULL_ADDER_INPUT_COUNT == 2:
 328             # Just pass the terms to the next layer, since we wouldn't gain
 329             # anything by using a half adder since there would still be 2 terms
 330             # and just passing the terms to the next layer saves gates.
 331             add_intermediate_term(self._resized_inputs[-2])
 332             add_intermediate_term(self._resized_inputs[-1])
 333         else:
 334             assert len(self.inputs) % FULL_ADDER_INPUT_COUNT == 0
 335         # recursive invocation of ``AddReduce``
 336         next_level = AddReduce(intermediate_terms,
 337                                len(self.output),
 338                                self.next_register_levels(),
 339                                self._reg_partition_points)
 340         m.submodules.next_level = next_level
 341         m.d.comb += self.output.eq(next_level.output)
 342         return m
 343
 344
 345 OP_MUL_LOW = 0
 346 OP_MUL_SIGNED_HIGH = 1
 347 OP_MUL_SIGNED_UNSIGNED_HIGH = 2  # a is signed, b is unsigned
 348 OP_MUL_UNSIGNED_HIGH = 3
 349
 350
 351 class Mul8_16_32_64(Elaboratable):
 352     """Signed/Unsigned 8/16/32/64-bit partitioned integer multiplier.
 353
 354     Supports partitioning into any combination of 8, 16, 32, and 64-bit
 355     partitions on naturally-aligned boundaries. Supports the operation being
 356     set for each partition independently.
 357
 358     :attribute part_pts: the input partition points. Has a partition point at
 359         multiples of 8 in 0 < i < 64. Each partition point's associated
 360         ``Value`` is a ``Signal``. Modification not supported, except for by
 361         ``Signal.eq``.
 362     :attribute part_ops: the operation for each byte. The operation for a
 363         particular partition is selected by assigning the selected operation
 364         code to each byte in the partition. The allowed operation codes are:
 365
 366         :attribute OP_MUL_LOW: the LSB half of the product. Equivalent to
 367             RISC-V's `mul` instruction.
 368         :attribute OP_MUL_SIGNED_HIGH: the MSB half of the product where both
 369             ``a`` and ``b`` are signed. Equivalent to RISC-V's `mulh`
 370             instruction.
 371         :attribute OP_MUL_SIGNED_UNSIGNED_HIGH: the MSB half of the product
 372             where ``a`` is signed and ``b`` is unsigned. Equivalent to RISC-V's
 373             `mulhsu` instruction.
 374         :attribute OP_MUL_UNSIGNED_HIGH: the MSB half of the product where both
 375             ``a`` and ``b`` are unsigned. Equivalent to RISC-V's `mulhu`
 376             instruction.
 377     """
 378
 379     def __init__(self, register_levels= ()):
 380         self.part_pts = PartitionPoints()
 381         for i in range(8, 64, 8):
 382             self.part_pts[i] = Signal(name=f"part_pts_{i}")
 383         self.part_ops = [Signal(2, name=f"part_ops_{i}") for i in range(8)]
 384         self.a = Signal(64)
 385         self.b = Signal(64)
 386         self.output = Signal(64)
 387         self.register_levels = list(register_levels)
 388         self._intermediate_output = Signal(128)
 389         self._delayed_part_ops = [
 390             [Signal(2, name=f"_delayed_part_ops_{delay}_{i}")
 391              for i in range(8)]
 392             for delay in range(1 + len(self.register_levels))]
 393         self._part_8 = [Signal(name=f"_part_8_{i}") for i in range(8)]
 394         self._part_16 = [Signal(name=f"_part_16_{i}") for i in range(4)]
 395         self._part_32 = [Signal(name=f"_part_32_{i}") for i in range(2)]
 396         self._part_64 = [Signal(name=f"_part_64")]
 397         self._delayed_part_8 = [
 398             [Signal(name=f"_delayed_part_8_{delay}_{i}")
 399              for i in range(8)]
 400             for delay in range(1 + len(self.register_levels))]
 401         self._delayed_part_16 = [
 402             [Signal(name=f"_delayed_part_16_{delay}_{i}")
 403              for i in range(4)]
 404             for delay in range(1 + len(self.register_levels))]
 405         self._delayed_part_32 = [
 406             [Signal(name=f"_delayed_part_32_{delay}_{i}")
 407              for i in range(2)]
 408             for delay in range(1 + len(self.register_levels))]
 409         self._delayed_part_64 = [
 410             [Signal(name=f"_delayed_part_64_{delay}")]
 411             for delay in range(1 + len(self.register_levels))]
 412         self._output_64 = Signal(64)
 413         self._output_32 = Signal(64)
 414         self._output_16 = Signal(64)
 415         self._output_8 = Signal(64)
 416         self._a_signed = [Signal(name=f"_a_signed_{i}") for i in range(8)]
 417         self._b_signed = [Signal(name=f"_b_signed_{i}") for i in range(8)]
 418         self._not_a_term_8 = Signal(128)
 419         self._neg_lsb_a_term_8 = Signal(128)
 420         self._not_b_term_8 = Signal(128)
 421         self._neg_lsb_b_term_8 = Signal(128)
 422         self._not_a_term_16 = Signal(128)
 423         self._neg_lsb_a_term_16 = Signal(128)
 424         self._not_b_term_16 = Signal(128)
 425         self._neg_lsb_b_term_16 = Signal(128)
 426         self._not_a_term_32 = Signal(128)
 427         self._neg_lsb_a_term_32 = Signal(128)
 428         self._not_b_term_32 = Signal(128)
 429         self._neg_lsb_b_term_32 = Signal(128)
 430         self._not_a_term_64 = Signal(128)
 431         self._neg_lsb_a_term_64 = Signal(128)
 432         self._not_b_term_64 = Signal(128)
 433         self._neg_lsb_b_term_64 = Signal(128)
 434
 435     def _part_byte(self, index):
 436         if index == -1 or index == 7:
 437             return C(True, 1)
 438         assert index >= 0 and index < 8
 439         return self.part_pts[index * 8 + 8]
 440
 441     def elaborate(self, platform):
 442         m = Module()
 443
 444         for i in range(len(self.part_ops)):
 445             m.d.comb += self._delayed_part_ops[0][i].eq(self.part_ops[i])
 446             m.d.sync += [self._delayed_part_ops[j + 1][i]
 447                          .eq(self._delayed_part_ops[j][i])
 448                          for j in range(len(self.register_levels))]
 449
 450         for parts, delayed_parts in [(self._part_64, self._delayed_part_64),
 451                                      (self._part_32, self._delayed_part_32),
 452                                      (self._part_16, self._delayed_part_16),
 453                                      (self._part_8, self._delayed_part_8)]:
 454             byte_count = 8 // len(parts)
 455             for i in range(len(parts)):
 456                 value = self._part_byte(i * byte_count - 1)
 457                 for j in range(i * byte_count, (i + 1) * byte_count - 1):
 458                     value &= ~self._part_byte(j)
 459                 value &= self._part_byte((i + 1) * byte_count - 1)
 460                 m.d.comb += parts[i].eq(value)
 461                 m.d.comb += delayed_parts[0][i].eq(parts[i])
 462                 m.d.sync += [delayed_parts[j + 1][i].eq(delayed_parts[j][i])
 463                              for j in range(len(self.register_levels))]
 464
 465         products = [[
 466                 Signal(16, name=f"products_{i}_{j}")
 467                 for j in range(8)]
 468             for i in range(8)]
 469
 470         for a_index in range(8):
 471             for b_index in range(8):
 472                 a = self.a.part(a_index * 8, 8)
 473                 b = self.b.part(b_index * 8, 8)
 474                 m.d.comb += products[a_index][b_index].eq(a * b)
 475
 476         terms = []
 477
 478         def add_term(value, shift=0, enabled=None):
 479             term = Signal(128)
 480             terms.append(term)
 481             if enabled is not None:
 482                 value = Mux(enabled, value, 0)
 483             if shift > 0:
 484                 value = Cat(Repl(C(0, 1), shift), value)
 485             else:
 486                 assert shift == 0
 487             m.d.comb += term.eq(value)
 488
 489         for a_index in range(8):
 490             for b_index in range(8):
 491                 term_enabled: Value = C(True, 1)
 492                 min_index = min(a_index, b_index)
 493                 max_index = max(a_index, b_index)
 494                 for i in range(min_index, max_index):
 495                     term_enabled &= ~self._part_byte(i)
 496                 add_term(products[a_index][b_index],
 497                          8 * (a_index + b_index),
 498                          term_enabled)
 499
 500         for i in range(8):
 501             a_signed = self.part_ops[i] != OP_MUL_UNSIGNED_HIGH
 502             b_signed = (self.part_ops[i] == OP_MUL_LOW) \
 503                 | (self.part_ops[i] == OP_MUL_SIGNED_HIGH)
 504             m.d.comb += self._a_signed[i].eq(a_signed)
 505             m.d.comb += self._b_signed[i].eq(b_signed)
 506
 507         # it's fine to bitwise-or these together since they are never enabled
 508         # at the same time
 509         add_term(self._not_a_term_8 | self._not_a_term_16
 510                  | self._not_a_term_32 | self._not_a_term_64)
 511         add_term(self._neg_lsb_a_term_8 | self._neg_lsb_a_term_16
 512                  | self._neg_lsb_a_term_32 | self._neg_lsb_a_term_64)
 513         add_term(self._not_b_term_8 | self._not_b_term_16
 514                  | self._not_b_term_32 | self._not_b_term_64)
 515         add_term(self._neg_lsb_b_term_8 | self._neg_lsb_b_term_16
 516                  | self._neg_lsb_b_term_32 | self._neg_lsb_b_term_64)
 517
 518         for not_a_term, \
 519             neg_lsb_a_term, \
 520             not_b_term, \
 521             neg_lsb_b_term, \
 522             parts in [
 523                 (self._not_a_term_8,
 524                  self._neg_lsb_a_term_8,
 525                  self._not_b_term_8,
 526                  self._neg_lsb_b_term_8,
 527                  self._part_8),
 528                 (self._not_a_term_16,
 529                  self._neg_lsb_a_term_16,
 530                  self._not_b_term_16,
 531                  self._neg_lsb_b_term_16,
 532                  self._part_16),
 533                 (self._not_a_term_32,
 534                  self._neg_lsb_a_term_32,
 535                  self._not_b_term_32,
 536                  self._neg_lsb_b_term_32,
 537                  self._part_32),
 538                 (self._not_a_term_64,
 539                  self._neg_lsb_a_term_64,
 540                  self._not_b_term_64,
 541                  self._neg_lsb_b_term_64,
 542                  self._part_64),
 543                 ]:
 544             byte_width = 8 // len(parts)
 545             bit_width = 8 * byte_width
 546             for i in range(len(parts)):
 547                 b_enabled = parts[i] & self.a[(i + 1) * bit_width - 1] \
 548                     & self._a_signed[i * byte_width]
 549                 a_enabled = parts[i] & self.b[(i + 1) * bit_width - 1] \
 550                     & self._b_signed[i * byte_width]
 551
 552                 # for 8-bit values: form a * 0xFF00 by using -a * 0x100, the
 553                 # negation operation is split into a bitwise not and a +1.
 554                 # likewise for 16, 32, and 64-bit values.
 555                 m.d.comb += [
 556                     not_a_term.part(bit_width * 2 * i, bit_width * 2)
 557                     .eq(Mux(a_enabled,
 558                             Cat(Repl(0, bit_width),
 559                                 ~self.a.part(bit_width * i, bit_width)),
 560                             0)),
 561
 562                     neg_lsb_a_term.part(bit_width * 2 * i, bit_width * 2)
 563                     .eq(Cat(Repl(0, bit_width), a_enabled)),
 564
 565                     not_b_term.part(bit_width * 2 * i, bit_width * 2)
 566                     .eq(Mux(b_enabled,
 567                             Cat(Repl(0, bit_width),
 568                                 ~self.b.part(bit_width * i, bit_width)),
 569                             0)),
 570
 571                     neg_lsb_b_term.part(bit_width * 2 * i, bit_width * 2)
 572                     .eq(Cat(Repl(0, bit_width), b_enabled))]
 573
 574         expanded_part_pts = PartitionPoints()
 575         for i, v in self.part_pts.items():
 576             signal = Signal(name=f"expanded_part_pts_{i*2}")
 577             expanded_part_pts[i * 2] = signal
 578             m.d.comb += signal.eq(v)
 579
 580         add_reduce = AddReduce(terms,
 581                                128,
 582                                self.register_levels,
 583                                expanded_part_pts)
 584         m.submodules.add_reduce = add_reduce
 585         m.d.comb += self._intermediate_output.eq(add_reduce.output)
 586         m.d.comb += self._output_64.eq(
 587             Mux(self._delayed_part_ops[-1][0] == OP_MUL_LOW,
 588                 self._intermediate_output.part(0, 64),
 589                 self._intermediate_output.part(64, 64)))
 590         for i in range(2):
 591             m.d.comb += self._output_32.part(i * 32, 32).eq(
 592                 Mux(self._delayed_part_ops[-1][4 * i] == OP_MUL_LOW,
 593                     self._intermediate_output.part(i * 64, 32),
 594                     self._intermediate_output.part(i * 64 + 32, 32)))
 595         for i in range(4):
 596             m.d.comb += self._output_16.part(i * 16, 16).eq(
 597                 Mux(self._delayed_part_ops[-1][2 * i] == OP_MUL_LOW,
 598                     self._intermediate_output.part(i * 32, 16),
 599                     self._intermediate_output.part(i * 32 + 16, 16)))
 600         for i in range(8):
 601             m.d.comb += self._output_8.part(i * 8, 8).eq(
 602                 Mux(self._delayed_part_ops[-1][i] == OP_MUL_LOW,
 603                     self._intermediate_output.part(i * 16, 8),
 604                     self._intermediate_output.part(i * 16 + 8, 8)))
 605         for i in range(8):
 606             m.d.comb += self.output.part(i * 8, 8).eq(
 607                 Mux(self._delayed_part_8[-1][i]
 608                     | self._delayed_part_16[-1][i // 2],
 609                     Mux(self._delayed_part_8[-1][i],
 610                         self._output_8.part(i * 8, 8),
 611                         self._output_16.part(i * 8, 8)),
 612                     Mux(self._delayed_part_32[-1][i // 4],
 613                         self._output_32.part(i * 8, 8),
 614                         self._output_64.part(i * 8, 8))))
 615         return m
 616
 617
 618 if __name__ == "__main__":
 619     m = Mul8_16_32_64()
 620     main(m, ports=[m.a,
 621                    m.b,
 622                    m._intermediate_output,
 623                    m.output,
 624                    *m.part_ops,
 625                    *m.part_pts.values()])