src/ieee754/part_mul_add/multiply.py

   1 # SPDX-License-Identifier: LGPL-2.1-or-later
   2 # See Notices.txt for copyright information
   3 """Integer Multiplication."""
   4
   5 from nmigen import Signal, Module, Value, Elaboratable, Cat, C, Mux, Repl
   6 from nmigen.hdl.ast import Assign
   7 from abc import ABCMeta, abstractmethod
   8 from nmigen.cli import main
   9
  10
  11 class PartitionPoints(dict):
  12     """Partition points and corresponding ``Value``s.
  13
  14     The points at where an ALU is partitioned along with ``Value``s that
  15     specify if the corresponding partition points are enabled.
  16
  17     For example: ``{1: True, 5: True, 10: True}`` with
  18     ``width == 16`` specifies that the ALU is split into 4 sections:
  19     * bits 0 <= ``i`` < 1
  20     * bits 1 <= ``i`` < 5
  21     * bits 5 <= ``i`` < 10
  22     * bits 10 <= ``i`` < 16
  23
  24     If the partition_points were instead ``{1: True, 5: a, 10: True}``
  25     where ``a`` is a 1-bit ``Signal``:
  26     * If ``a`` is asserted:
  27         * bits 0 <= ``i`` < 1
  28         * bits 1 <= ``i`` < 5
  29         * bits 5 <= ``i`` < 10
  30         * bits 10 <= ``i`` < 16
  31     * Otherwise
  32         * bits 0 <= ``i`` < 1
  33         * bits 1 <= ``i`` < 10
  34         * bits 10 <= ``i`` < 16
  35     """
  36
  37     def __init__(self, partition_points=None):
  38         """Create a new ``PartitionPoints``.
  39
  40         :param partition_points: the input partition points to values mapping.
  41         """
  42         super().__init__()
  43         if partition_points is not None:
  44             for point, enabled in partition_points.items():
  45                 if not isinstance(point, int):
  46                     raise TypeError("point must be a non-negative integer")
  47                 if point < 0:
  48                     raise ValueError("point must be a non-negative integer")
  49                 self[point] = Value.wrap(enabled)
  50
  51     def like(self, name=None, src_loc_at=0):
  52         """Create a new ``PartitionPoints`` with ``Signal``s for all values.
  53
  54         :param name: the base name for the new ``Signal``s.
  55         """
  56         if name is None:
  57             name = Signal(src_loc_at=1+src_loc_at).name  # get variable name
  58         retval = PartitionPoints()
  59         for point, enabled in self.items():
  60             retval[point] = Signal(enabled.shape(), name=f"{name}_{point}")
  61         return retval
  62
  63     def eq(self, rhs):
  64         """Assign ``PartitionPoints`` using ``Signal.eq``."""
  65         if set(self.keys()) != set(rhs.keys()):
  66             raise ValueError("incompatible point set")
  67         for point, enabled in self.items():
  68             yield enabled.eq(rhs[point])
  69
  70     def as_mask(self, width):
  71         """Create a bit-mask from `self`.
  72
  73         Each bit in the returned mask is clear only if the partition point at
  74         the same bit-index is enabled.
  75
  76         :param width: the bit width of the resulting mask
  77         """
  78         bits = []
  79         for i in range(width):
  80             if i in self:
  81                 bits.append(~self[i])
  82             else:
  83                 bits.append(True)
  84         return Cat(*bits)
  85
  86     def get_max_partition_count(self, width):
  87         """Get the maximum number of partitions.
  88
  89         Gets the number of partitions when all partition points are enabled.
  90         """
  91         retval = 1
  92         for point in self.keys():
  93             if point < width:
  94                 retval += 1
  95         return retval
  96
  97     def fits_in_width(self, width):
  98         """Check if all partition points are smaller than `width`."""
  99         for point in self.keys():
 100             if point >= width:
 101                 return False
 102         return True
 103
 104
 105 class FullAdder(Elaboratable):
 106     """Full Adder.
 107
 108     :attribute in0: the first input
 109     :attribute in1: the second input
 110     :attribute in2: the third input
 111     :attribute sum: the sum output
 112     :attribute carry: the carry output
 113     """
 114
 115     def __init__(self, width):
 116         """Create a ``FullAdder``.
 117
 118         :param width: the bit width of the input and output
 119         """
 120         self.in0 = Signal(width)
 121         self.in1 = Signal(width)
 122         self.in2 = Signal(width)
 123         self.sum = Signal(width)
 124         self.carry = Signal(width)
 125
 126     def elaborate(self, platform):
 127         """Elaborate this module."""
 128         m = Module()
 129         m.d.comb += self.sum.eq(self.in0 ^ self.in1 ^ self.in2)
 130         m.d.comb += self.carry.eq((self.in0 & self.in1)
 131                                   | (self.in1 & self.in2)
 132                                   | (self.in2 & self.in0))
 133         return m
 134
 135
 136 class PartitionedAdder(Elaboratable):
 137     """Partitioned Adder.
 138
 139     :attribute width: the bit width of the input and output. Read-only.
 140     :attribute a: the first input to the adder
 141     :attribute b: the second input to the adder
 142     :attribute output: the sum output
 143     :attribute partition_points: the input partition points. Modification not
 144         supported, except for by ``Signal.eq``.
 145     """
 146
 147     def __init__(self, width, partition_points):
 148         """Create a ``PartitionedAdder``.
 149
 150         :param width: the bit width of the input and output
 151         :param partition_points: the input partition points
 152         """
 153         self.width = width
 154         self.a = Signal(width)
 155         self.b = Signal(width)
 156         self.output = Signal(width)
 157         self.partition_points = PartitionPoints(partition_points)
 158         if not self.partition_points.fits_in_width(width):
 159             raise ValueError("partition_points doesn't fit in width")
 160         expanded_width = 0
 161         for i in range(self.width):
 162             if i in self.partition_points:
 163                 expanded_width += 1
 164             expanded_width += 1
 165         self._expanded_width = expanded_width
 166         self._expanded_a = Signal(expanded_width)
 167         self._expanded_b = Signal(expanded_width)
 168         self._expanded_output = Signal(expanded_width)
 169
 170     def elaborate(self, platform):
 171         """Elaborate this module."""
 172         m = Module()
 173         expanded_index = 0
 174         # store bits in a list, use Cat later.  graphviz is much cleaner
 175         al = []
 176         bl = []
 177         ol = []
 178         ea = []
 179         eb = []
 180         eo = []
 181         # partition points are "breaks" (extra zeros) in what would otherwise
 182         # be a massive long add.
 183         for i in range(self.width):
 184             if i in self.partition_points:
 185                 # add extra bit set to 0 + 0 for enabled partition points
 186                 # and 1 + 0 for disabled partition points
 187                 ea.append(self._expanded_a[expanded_index])
 188                 al.append(~self.partition_points[i])
 189                 eb.append(self._expanded_b[expanded_index])
 190                 bl.append(C(0))
 191                 expanded_index += 1
 192             ea.append(self._expanded_a[expanded_index])
 193             al.append(self.a[i])
 194             eb.append(self._expanded_b[expanded_index])
 195             bl.append(self.b[i])
 196             eo.append(self._expanded_output[expanded_index])
 197             ol.append(self.output[i])
 198             expanded_index += 1
 199         # combine above using Cat
 200         m.d.comb += Cat(*ea).eq(Cat(*al))
 201         m.d.comb += Cat(*eb).eq(Cat(*bl))
 202         m.d.comb += Cat(*eo).eq(Cat(*ol))
 203         # use only one addition to take advantage of look-ahead carry and
 204         # special hardware on FPGAs
 205         m.d.comb += self._expanded_output.eq(
 206             self._expanded_a + self._expanded_b)
 207         return m
 208
 209
 210 FULL_ADDER_INPUT_COUNT = 3
 211
 212
 213 class AddReduce(Elaboratable):
 214     """Add list of numbers together.
 215
 216     :attribute inputs: input ``Signal``s to be summed. Modification not
 217         supported, except for by ``Signal.eq``.
 218     :attribute register_levels: List of nesting levels that should have
 219         pipeline registers.
 220     :attribute output: output sum.
 221     :attribute partition_points: the input partition points. Modification not
 222         supported, except for by ``Signal.eq``.
 223     """
 224
 225     def __init__(self, inputs, output_width, register_levels, partition_points):
 226         """Create an ``AddReduce``.
 227
 228         :param inputs: input ``Signal``s to be summed.
 229         :param output_width: bit-width of ``output``.
 230         :param register_levels: List of nesting levels that should have
 231             pipeline registers.
 232         :param partition_points: the input partition points.
 233         """
 234         self.inputs = list(inputs)
 235         self._resized_inputs = [
 236             Signal(output_width, name=f"resized_inputs[{i}]")
 237             for i in range(len(self.inputs))]
 238         self.register_levels = list(register_levels)
 239         self.output = Signal(output_width)
 240         self.partition_points = PartitionPoints(partition_points)
 241         if not self.partition_points.fits_in_width(output_width):
 242             raise ValueError("partition_points doesn't fit in output_width")
 243         self._reg_partition_points = self.partition_points.like()
 244         max_level = AddReduce.get_max_level(len(self.inputs))
 245         for level in self.register_levels:
 246             if level > max_level:
 247                 raise ValueError(
 248                     "not enough adder levels for specified register levels")
 249
 250     @staticmethod
 251     def get_max_level(input_count):
 252         """Get the maximum level.
 253
 254         All ``register_levels`` must be less than or equal to the maximum
 255         level.
 256         """
 257         retval = 0
 258         while True:
 259             groups = AddReduce.full_adder_groups(input_count)
 260             if len(groups) == 0:
 261                 return retval
 262             input_count %= FULL_ADDER_INPUT_COUNT
 263             input_count += 2 * len(groups)
 264             retval += 1
 265
 266     def next_register_levels(self):
 267         """``Iterable`` of ``register_levels`` for next recursive level."""
 268         for level in self.register_levels:
 269             if level > 0:
 270                 yield level - 1
 271
 272     @staticmethod
 273     def full_adder_groups(input_count):
 274         """Get ``inputs`` indices for which a full adder should be built."""
 275         return range(0,
 276                      input_count - FULL_ADDER_INPUT_COUNT + 1,
 277                      FULL_ADDER_INPUT_COUNT)
 278
 279     def elaborate(self, platform):
 280         """Elaborate this module."""
 281         m = Module()
 282
 283         # resize inputs to correct bit-width and optionally add in
 284         # pipeline registers
 285         resized_input_assignments = [self._resized_inputs[i].eq(self.inputs[i])
 286                                      for i in range(len(self.inputs))]
 287         if 0 in self.register_levels:
 288             m.d.sync += resized_input_assignments
 289             m.d.sync += self._reg_partition_points.eq(self.partition_points)
 290         else:
 291             m.d.comb += resized_input_assignments
 292             m.d.comb += self._reg_partition_points.eq(self.partition_points)
 293
 294         groups = AddReduce.full_adder_groups(len(self.inputs))
 295         # if there are no full adders to create, then we handle the base cases
 296         # and return, otherwise we go on to the recursive case
 297         if len(groups) == 0:
 298             if len(self.inputs) == 0:
 299                 # use 0 as the default output value
 300                 m.d.comb += self.output.eq(0)
 301             elif len(self.inputs) == 1:
 302                 # handle single input
 303                 m.d.comb += self.output.eq(self._resized_inputs[0])
 304             else:
 305                 # base case for adding 2 or more inputs, which get recursively
 306                 # reduced to 2 inputs
 307                 assert len(self.inputs) == 2
 308                 adder = PartitionedAdder(len(self.output),
 309                                          self._reg_partition_points)
 310                 m.submodules.final_adder = adder
 311                 m.d.comb += adder.a.eq(self._resized_inputs[0])
 312                 m.d.comb += adder.b.eq(self._resized_inputs[1])
 313                 m.d.comb += self.output.eq(adder.output)
 314             return m
 315         # go on to handle recursive case
 316         intermediate_terms: List[Signal]
 317         intermediate_terms = []
 318
 319         def add_intermediate_term(value):
 320             intermediate_term = Signal(
 321                 len(self.output),
 322                 name=f"intermediate_terms[{len(intermediate_terms)}]")
 323             intermediate_terms.append(intermediate_term)
 324             m.d.comb += intermediate_term.eq(value)
 325
 326         # store mask in intermediary (simplifies graph)
 327         part_mask = Signal(len(self.output), reset_less=True)
 328         mask = self._reg_partition_points.as_mask(len(self.output))
 329         m.d.comb += part_mask.eq(mask)
 330
 331         # create full adders for this recursive level.
 332         # this shrinks N terms to 2 * (N // 3) plus the remainder
 333         for i in groups:
 334             adder_i = FullAdder(len(self.output))
 335             setattr(m.submodules, f"adder_{i}", adder_i)
 336             m.d.comb += adder_i.in0.eq(self._resized_inputs[i])
 337             m.d.comb += adder_i.in1.eq(self._resized_inputs[i + 1])
 338             m.d.comb += adder_i.in2.eq(self._resized_inputs[i + 2])
 339             add_intermediate_term(adder_i.sum)
 340             shifted_carry = adder_i.carry << 1
 341             # mask out carry bits to prevent carries between partitions
 342             add_intermediate_term((adder_i.carry << 1) & part_mask)
 343         # handle the remaining inputs.
 344         if len(self.inputs) % FULL_ADDER_INPUT_COUNT == 1:
 345             add_intermediate_term(self._resized_inputs[-1])
 346         elif len(self.inputs) % FULL_ADDER_INPUT_COUNT == 2:
 347             # Just pass the terms to the next layer, since we wouldn't gain
 348             # anything by using a half adder since there would still be 2 terms
 349             # and just passing the terms to the next layer saves gates.
 350             add_intermediate_term(self._resized_inputs[-2])
 351             add_intermediate_term(self._resized_inputs[-1])
 352         else:
 353             assert len(self.inputs) % FULL_ADDER_INPUT_COUNT == 0
 354         # recursive invocation of ``AddReduce``
 355         next_level = AddReduce(intermediate_terms,
 356                                len(self.output),
 357                                self.next_register_levels(),
 358                                self._reg_partition_points)
 359         m.submodules.next_level = next_level
 360         m.d.comb += self.output.eq(next_level.output)
 361         return m
 362
 363
 364 OP_MUL_LOW = 0
 365 OP_MUL_SIGNED_HIGH = 1
 366 OP_MUL_SIGNED_UNSIGNED_HIGH = 2  # a is signed, b is unsigned
 367 OP_MUL_UNSIGNED_HIGH = 3
 368
 369
 370 class Mul8_16_32_64(Elaboratable):
 371     """Signed/Unsigned 8/16/32/64-bit partitioned integer multiplier.
 372
 373     Supports partitioning into any combination of 8, 16, 32, and 64-bit
 374     partitions on naturally-aligned boundaries. Supports the operation being
 375     set for each partition independently.
 376
 377     :attribute part_pts: the input partition points. Has a partition point at
 378         multiples of 8 in 0 < i < 64. Each partition point's associated
 379         ``Value`` is a ``Signal``. Modification not supported, except for by
 380         ``Signal.eq``.
 381     :attribute part_ops: the operation for each byte. The operation for a
 382         particular partition is selected by assigning the selected operation
 383         code to each byte in the partition. The allowed operation codes are:
 384
 385         :attribute OP_MUL_LOW: the LSB half of the product. Equivalent to
 386             RISC-V's `mul` instruction.
 387         :attribute OP_MUL_SIGNED_HIGH: the MSB half of the product where both
 388             ``a`` and ``b`` are signed. Equivalent to RISC-V's `mulh`
 389             instruction.
 390         :attribute OP_MUL_SIGNED_UNSIGNED_HIGH: the MSB half of the product
 391             where ``a`` is signed and ``b`` is unsigned. Equivalent to RISC-V's
 392             `mulhsu` instruction.
 393         :attribute OP_MUL_UNSIGNED_HIGH: the MSB half of the product where both
 394             ``a`` and ``b`` are unsigned. Equivalent to RISC-V's `mulhu`
 395             instruction.
 396     """
 397
 398     def __init__(self, register_levels= ()):
 399         self.part_pts = PartitionPoints()
 400         for i in range(8, 64, 8):
 401             self.part_pts[i] = Signal(name=f"part_pts_{i}")
 402         self.part_ops = [Signal(2, name=f"part_ops_{i}") for i in range(8)]
 403         self.a = Signal(64)
 404         self.b = Signal(64)
 405         self.output = Signal(64)
 406         self.register_levels = list(register_levels)
 407         self._intermediate_output = Signal(128)
 408         self._delayed_part_ops = [
 409             [Signal(2, name=f"_delayed_part_ops_{delay}_{i}")
 410              for i in range(8)]
 411             for delay in range(1 + len(self.register_levels))]
 412         self._part_8 = [Signal(name=f"_part_8_{i}") for i in range(8)]
 413         self._part_16 = [Signal(name=f"_part_16_{i}") for i in range(4)]
 414         self._part_32 = [Signal(name=f"_part_32_{i}") for i in range(2)]
 415         self._part_64 = [Signal(name=f"_part_64")]
 416         self._delayed_part_8 = [
 417             [Signal(name=f"_delayed_part_8_{delay}_{i}")
 418              for i in range(8)]
 419             for delay in range(1 + len(self.register_levels))]
 420         self._delayed_part_16 = [
 421             [Signal(name=f"_delayed_part_16_{delay}_{i}")
 422              for i in range(4)]
 423             for delay in range(1 + len(self.register_levels))]
 424         self._delayed_part_32 = [
 425             [Signal(name=f"_delayed_part_32_{delay}_{i}")
 426              for i in range(2)]
 427             for delay in range(1 + len(self.register_levels))]
 428         self._delayed_part_64 = [
 429             [Signal(name=f"_delayed_part_64_{delay}")]
 430             for delay in range(1 + len(self.register_levels))]
 431         self._output_64 = Signal(64)
 432         self._output_32 = Signal(64)
 433         self._output_16 = Signal(64)
 434         self._output_8 = Signal(64)
 435         self._a_signed = [Signal(name=f"_a_signed_{i}") for i in range(8)]
 436         self._b_signed = [Signal(name=f"_b_signed_{i}") for i in range(8)]
 437         self._not_a_term_8 = Signal(128)
 438         self._neg_lsb_a_term_8 = Signal(128)
 439         self._not_b_term_8 = Signal(128)
 440         self._neg_lsb_b_term_8 = Signal(128)
 441         self._not_a_term_16 = Signal(128)
 442         self._neg_lsb_a_term_16 = Signal(128)
 443         self._not_b_term_16 = Signal(128)
 444         self._neg_lsb_b_term_16 = Signal(128)
 445         self._not_a_term_32 = Signal(128)
 446         self._neg_lsb_a_term_32 = Signal(128)
 447         self._not_b_term_32 = Signal(128)
 448         self._neg_lsb_b_term_32 = Signal(128)
 449         self._not_a_term_64 = Signal(128)
 450         self._neg_lsb_a_term_64 = Signal(128)
 451         self._not_b_term_64 = Signal(128)
 452         self._neg_lsb_b_term_64 = Signal(128)
 453
 454     def _part_byte(self, index):
 455         if index == -1 or index == 7:
 456             return C(True, 1)
 457         assert index >= 0 and index < 8
 458         return self.part_pts[index * 8 + 8]
 459
 460     def elaborate(self, platform):
 461         m = Module()
 462
 463         for i in range(len(self.part_ops)):
 464             m.d.comb += self._delayed_part_ops[0][i].eq(self.part_ops[i])
 465             m.d.sync += [self._delayed_part_ops[j + 1][i]
 466                          .eq(self._delayed_part_ops[j][i])
 467                          for j in range(len(self.register_levels))]
 468
 469         for parts, delayed_parts in [(self._part_64, self._delayed_part_64),
 470                                      (self._part_32, self._delayed_part_32),
 471                                      (self._part_16, self._delayed_part_16),
 472                                      (self._part_8, self._delayed_part_8)]:
 473             byte_count = 8 // len(parts)
 474             for i in range(len(parts)):
 475                 value = self._part_byte(i * byte_count - 1)
 476                 for j in range(i * byte_count, (i + 1) * byte_count - 1):
 477                     value &= ~self._part_byte(j)
 478                 value &= self._part_byte((i + 1) * byte_count - 1)
 479                 m.d.comb += parts[i].eq(value)
 480                 m.d.comb += delayed_parts[0][i].eq(parts[i])
 481                 m.d.sync += [delayed_parts[j + 1][i].eq(delayed_parts[j][i])
 482                              for j in range(len(self.register_levels))]
 483
 484         products = [[
 485                 Signal(16, name=f"products_{i}_{j}")
 486                 for j in range(8)]
 487             for i in range(8)]
 488
 489         for a_index in range(8):
 490             for b_index in range(8):
 491                 a = self.a.part(a_index * 8, 8)
 492                 b = self.b.part(b_index * 8, 8)
 493                 m.d.comb += products[a_index][b_index].eq(a * b)
 494
 495         terms = []
 496
 497         def add_term(value, shift=0, enabled=None):
 498             term = Signal(128)
 499             terms.append(term)
 500             if enabled is not None:
 501                 value = Mux(enabled, value, 0)
 502             if shift > 0:
 503                 value = Cat(Repl(C(0, 1), shift), value)
 504             else:
 505                 assert shift == 0
 506             m.d.comb += term.eq(value)
 507
 508         for a_index in range(8):
 509             for b_index in range(8):
 510                 term_enabled: Value = C(True, 1)
 511                 min_index = min(a_index, b_index)
 512                 max_index = max(a_index, b_index)
 513                 for i in range(min_index, max_index):
 514                     term_enabled &= ~self._part_byte(i)
 515                 add_term(products[a_index][b_index],
 516                          8 * (a_index + b_index),
 517                          term_enabled)
 518
 519         for i in range(8):
 520             a_signed = self.part_ops[i] != OP_MUL_UNSIGNED_HIGH
 521             b_signed = (self.part_ops[i] == OP_MUL_LOW) \
 522                 | (self.part_ops[i] == OP_MUL_SIGNED_HIGH)
 523             m.d.comb += self._a_signed[i].eq(a_signed)
 524             m.d.comb += self._b_signed[i].eq(b_signed)
 525
 526         # it's fine to bitwise-or these together since they are never enabled
 527         # at the same time
 528         add_term(self._not_a_term_8 | self._not_a_term_16
 529                  | self._not_a_term_32 | self._not_a_term_64)
 530         add_term(self._neg_lsb_a_term_8 | self._neg_lsb_a_term_16
 531                  | self._neg_lsb_a_term_32 | self._neg_lsb_a_term_64)
 532         add_term(self._not_b_term_8 | self._not_b_term_16
 533                  | self._not_b_term_32 | self._not_b_term_64)
 534         add_term(self._neg_lsb_b_term_8 | self._neg_lsb_b_term_16
 535                  | self._neg_lsb_b_term_32 | self._neg_lsb_b_term_64)
 536
 537         for not_a_term, \
 538             neg_lsb_a_term, \
 539             not_b_term, \
 540             neg_lsb_b_term, \
 541             parts in [
 542                 (self._not_a_term_8,
 543                  self._neg_lsb_a_term_8,
 544                  self._not_b_term_8,
 545                  self._neg_lsb_b_term_8,
 546                  self._part_8),
 547                 (self._not_a_term_16,
 548                  self._neg_lsb_a_term_16,
 549                  self._not_b_term_16,
 550                  self._neg_lsb_b_term_16,
 551                  self._part_16),
 552                 (self._not_a_term_32,
 553                  self._neg_lsb_a_term_32,
 554                  self._not_b_term_32,
 555                  self._neg_lsb_b_term_32,
 556                  self._part_32),
 557                 (self._not_a_term_64,
 558                  self._neg_lsb_a_term_64,
 559                  self._not_b_term_64,
 560                  self._neg_lsb_b_term_64,
 561                  self._part_64),
 562                 ]:
 563             byte_width = 8 // len(parts)
 564             bit_width = 8 * byte_width
 565             for i in range(len(parts)):
 566                 b_enabled = parts[i] & self.a[(i + 1) * bit_width - 1] \
 567                     & self._a_signed[i * byte_width]
 568                 a_enabled = parts[i] & self.b[(i + 1) * bit_width - 1] \
 569                     & self._b_signed[i * byte_width]
 570
 571                 # for 8-bit values: form a * 0xFF00 by using -a * 0x100, the
 572                 # negation operation is split into a bitwise not and a +1.
 573                 # likewise for 16, 32, and 64-bit values.
 574                 m.d.comb += [
 575                     not_a_term.part(bit_width * 2 * i, bit_width * 2)
 576                     .eq(Mux(a_enabled,
 577                             Cat(Repl(0, bit_width),
 578                                 ~self.a.part(bit_width * i, bit_width)),
 579                             0)),
 580
 581                     neg_lsb_a_term.part(bit_width * 2 * i, bit_width * 2)
 582                     .eq(Cat(Repl(0, bit_width), a_enabled)),
 583
 584                     not_b_term.part(bit_width * 2 * i, bit_width * 2)
 585                     .eq(Mux(b_enabled,
 586                             Cat(Repl(0, bit_width),
 587                                 ~self.b.part(bit_width * i, bit_width)),
 588                             0)),
 589
 590                     neg_lsb_b_term.part(bit_width * 2 * i, bit_width * 2)
 591                     .eq(Cat(Repl(0, bit_width), b_enabled))]
 592
 593         expanded_part_pts = PartitionPoints()
 594         for i, v in self.part_pts.items():
 595             signal = Signal(name=f"expanded_part_pts_{i*2}")
 596             expanded_part_pts[i * 2] = signal
 597             m.d.comb += signal.eq(v)
 598
 599         add_reduce = AddReduce(terms,
 600                                128,
 601                                self.register_levels,
 602                                expanded_part_pts)
 603         m.submodules.add_reduce = add_reduce
 604         m.d.comb += self._intermediate_output.eq(add_reduce.output)
 605         m.d.comb += self._output_64.eq(
 606             Mux(self._delayed_part_ops[-1][0] == OP_MUL_LOW,
 607                 self._intermediate_output.part(0, 64),
 608                 self._intermediate_output.part(64, 64)))
 609         for i in range(2):
 610             m.d.comb += self._output_32.part(i * 32, 32).eq(
 611                 Mux(self._delayed_part_ops[-1][4 * i] == OP_MUL_LOW,
 612                     self._intermediate_output.part(i * 64, 32),
 613                     self._intermediate_output.part(i * 64 + 32, 32)))
 614         for i in range(4):
 615             m.d.comb += self._output_16.part(i * 16, 16).eq(
 616                 Mux(self._delayed_part_ops[-1][2 * i] == OP_MUL_LOW,
 617                     self._intermediate_output.part(i * 32, 16),
 618                     self._intermediate_output.part(i * 32 + 16, 16)))
 619         for i in range(8):
 620             m.d.comb += self._output_8.part(i * 8, 8).eq(
 621                 Mux(self._delayed_part_ops[-1][i] == OP_MUL_LOW,
 622                     self._intermediate_output.part(i * 16, 8),
 623                     self._intermediate_output.part(i * 16 + 8, 8)))
 624         for i in range(8):
 625             m.d.comb += self.output.part(i * 8, 8).eq(
 626                 Mux(self._delayed_part_8[-1][i]
 627                     | self._delayed_part_16[-1][i // 2],
 628                     Mux(self._delayed_part_8[-1][i],
 629                         self._output_8.part(i * 8, 8),
 630                         self._output_16.part(i * 8, 8)),
 631                     Mux(self._delayed_part_32[-1][i // 4],
 632                         self._output_32.part(i * 8, 8),
 633                         self._output_64.part(i * 8, 8))))
 634         return m
 635
 636
 637 if __name__ == "__main__":
 638     m = Mul8_16_32_64()
 639     main(m, ports=[m.a,
 640                    m.b,
 641                    m._intermediate_output,
 642                    m.output,
 643                    *m.part_ops,
 644                    *m.part_pts.values()])