src/ieee754/part_shift/bitrev.py

   1 from nmigen import Signal, Module, Elaboratable, Cat, Mux
   2
   3 class GatedBitReverse(Elaboratable):
   4
   5     def __init__(self, width):
   6         self.width = width
   7         self.data = Signal(width, reset_less=True)
   8         self.reverse_en = Signal(reset_less=True)
   9         self.output = Signal(width, reset_less=True)
  10
  11     def elaborate(self, platform):
  12         m = Module()
  13         comb = m.d.comb
  14         width = self.width
  15
  16         l, r = [], []
  17         for i in range(width):
  18             l.append(self.data[i])
  19             r.append(self.data[width-i-1])
  20
  21         with m.If(self.reverse_en):
  22             comb += self.output.eq(Cat(*r))
  23         with m.Else():
  24             comb += self.output.eq(Cat(*l))
  25
  26         return m