src/nmutil/singlepipe.py

   1 """ Pipeline API.  For multi-input and multi-output variants, see multipipe.
   2
   3     Associated development bugs:
   4     * http://bugs.libre-riscv.org/show_bug.cgi?id=64
   5     * http://bugs.libre-riscv.org/show_bug.cgi?id=57
   6
   7     Important: see Stage API (stageapi.py) in combination with below
   8
   9     RecordBasedStage:
  10     ----------------
  11
  12     A convenience class that takes an input shape, output shape, a
  13     "processing" function and an optional "setup" function.  Honestly
  14     though, there's not much more effort to just... create a class
  15     that returns a couple of Records (see ExampleAddRecordStage in
  16     examples).
  17
  18     PassThroughStage:
  19     ----------------
  20
  21     A convenience class that takes a single function as a parameter,
  22     that is chain-called to create the exact same input and output spec.
  23     It has a process() function that simply returns its input.
  24
  25     Instances of this class are completely redundant if handed to
  26     StageChain, however when passed to UnbufferedPipeline they
  27     can be used to introduce a single clock delay.
  28
  29     ControlBase:
  30     -----------
  31
  32     The base class for pipelines.  Contains previous and next ready/valid/data.
  33     Also has an extremely useful "connect" function that can be used to
  34     connect a chain of pipelines and present the exact same prev/next
  35     ready/valid/data API.
  36
  37     Note: pipelines basically do not become pipelines as such until
  38     handed to a derivative of ControlBase.  ControlBase itself is *not*
  39     strictly considered a pipeline class.  Wishbone and AXI4 (master or
  40     slave) could be derived from ControlBase, for example.
  41     UnbufferedPipeline:
  42     ------------------
  43
  44     A simple stalling clock-synchronised pipeline that has no buffering
  45     (unlike BufferedHandshake).  Data flows on *every* clock cycle when
  46     the conditions are right (this is nominally when the input is valid
  47     and the output is ready).
  48
  49     A stall anywhere along the line will result in a stall back-propagating
  50     down the entire chain.  The BufferedHandshake by contrast will buffer
  51     incoming data, allowing previous stages one clock cycle's grace before
  52     also having to stall.
  53
  54     An advantage of the UnbufferedPipeline over the Buffered one is
  55     that the amount of logic needed (number of gates) is greatly
  56     reduced (no second set of buffers basically)
  57
  58     The disadvantage of the UnbufferedPipeline is that the valid/ready
  59     logic, if chained together, is *combinatorial*, resulting in
  60     progressively larger gate delay.
  61
  62     PassThroughHandshake:
  63     ------------------
  64
  65     A Control class that introduces a single clock delay, passing its
  66     data through unaltered.  Unlike RegisterPipeline (which relies
  67     on UnbufferedPipeline and PassThroughStage) it handles ready/valid
  68     itself.
  69
  70     RegisterPipeline:
  71     ----------------
  72
  73     A convenience class that, because UnbufferedPipeline introduces a single
  74     clock delay, when its stage is a PassThroughStage, it results in a Pipeline
  75     stage that, duh, delays its (unmodified) input by one clock cycle.
  76
  77     BufferedHandshake:
  78     ----------------
  79
  80     nmigen implementation of buffered pipeline stage, based on zipcpu:
  81     https://zipcpu.com/blog/2017/08/14/strategies-for-pipelining.html
  82
  83     this module requires quite a bit of thought to understand how it works
  84     (and why it is needed in the first place).  reading the above is
  85     *strongly* recommended.
  86
  87     unlike john dawson's IEEE754 FPU STB/ACK signalling, which requires
  88     the STB / ACK signals to raise and lower (on separate clocks) before
  89     data may proceeed (thus only allowing one piece of data to proceed
  90     on *ALTERNATE* cycles), the signalling here is a true pipeline
  91     where data will flow on *every* clock when the conditions are right.
  92
  93     input acceptance conditions are when:
  94         * incoming previous-stage strobe (p.valid_i) is HIGH
  95         * outgoing previous-stage ready   (p.ready_o) is LOW
  96
  97     output transmission conditions are when:
  98         * outgoing next-stage strobe (n.valid_o) is HIGH
  99         * outgoing next-stage ready   (n.ready_i) is LOW
 100
 101     the tricky bit is when the input has valid data and the output is not
 102     ready to accept it.  if it wasn't for the clock synchronisation, it
 103     would be possible to tell the input "hey don't send that data, we're
 104     not ready".  unfortunately, it's not possible to "change the past":
 105     the previous stage *has no choice* but to pass on its data.
 106
 107     therefore, the incoming data *must* be accepted - and stored: that
 108     is the responsibility / contract that this stage *must* accept.
 109     on the same clock, it's possible to tell the input that it must
 110     not send any more data.  this is the "stall" condition.
 111
 112     we now effectively have *two* possible pieces of data to "choose" from:
 113     the buffered data, and the incoming data.  the decision as to which
 114     to process and output is based on whether we are in "stall" or not.
 115     i.e. when the next stage is no longer ready, the output comes from
 116     the buffer if a stall had previously occurred, otherwise it comes
 117     direct from processing the input.
 118
 119     this allows us to respect a synchronous "travelling STB" with what
 120     dan calls a "buffered handshake".
 121
 122     it's quite a complex state machine!
 123
 124     SimpleHandshake
 125     ---------------
 126
 127     Synchronised pipeline, Based on:
 128     https://github.com/ZipCPU/dbgbus/blob/master/hexbus/rtl/hbdeword.v
 129 """
 130
 131 from nmigen import Signal, Mux, Module, Elaboratable
 132 from nmigen.cli import verilog, rtlil
 133 from nmigen.hdl.rec import Record
 134
 135 from nmutil.queue import Queue
 136 import inspect
 137
 138 from nmutil.iocontrol import (PrevControl, NextControl, Object, RecordObject)
 139 from nmutil.stageapi import (_spec, StageCls, Stage, StageChain, StageHelper)
 140 from nmutil import nmoperator
 141
 142
 143 class RecordBasedStage(Stage):
 144     """ convenience class which provides a Records-based layout.
 145         honestly it's a lot easier just to create a direct Records-based
 146         class (see ExampleAddRecordStage)
 147     """
 148     def __init__(self, in_shape, out_shape, processfn, setupfn=None):
 149         self.in_shape = in_shape
 150         self.out_shape = out_shape
 151         self.__process = processfn
 152         self.__setup = setupfn
 153     def ispec(self): return Record(self.in_shape)
 154     def ospec(self): return Record(self.out_shape)
 155     def process(seif, i): return self.__process(i)
 156     def setup(seif, m, i): return self.__setup(m, i)
 157
 158
 159 class PassThroughStage(StageCls):
 160     """ a pass-through stage with its input data spec identical to its output,
 161         and "passes through" its data from input to output (does nothing).
 162
 163         use this basically to explicitly make any data spec Stage-compliant.
 164         (many APIs would potentially use a static "wrap" method in e.g.
 165          StageCls to achieve a similar effect)
 166     """
 167     def __init__(self, iospecfn): self.iospecfn = iospecfn
 168     def ispec(self): return self.iospecfn()
 169     def ospec(self): return self.iospecfn()
 170
 171
 172 class ControlBase(StageHelper, Elaboratable):
 173     """ Common functions for Pipeline API.  Note: a "pipeline stage" only
 174         exists (conceptually) when a ControlBase derivative is handed
 175         a Stage (combinatorial block)
 176
 177         NOTE: ControlBase derives from StageHelper, making it accidentally
 178         compliant with the Stage API.  Using those functions directly
 179         *BYPASSES* a ControlBase instance ready/valid signalling, which
 180         clearly should not be done without a really, really good reason.
 181     """
 182     def __init__(self, stage=None, in_multi=None, stage_ctl=False):
 183         """ Base class containing ready/valid/data to previous and next stages
 184
 185             * p: contains ready/valid to the previous stage
 186             * n: contains ready/valid to the next stage
 187
 188             Except when calling Controlbase.connect(), user must also:
 189             * add data_i member to PrevControl (p) and
 190             * add data_o member to NextControl (n)
 191             Calling ControlBase._new_data is a good way to do that.
 192         """
 193         print ("ControlBase", self, stage, in_multi, stage_ctl)
 194         StageHelper.__init__(self, stage)
 195
 196         # set up input and output IO ACK (prev/next ready/valid)
 197         self.p = PrevControl(in_multi, stage_ctl)
 198         self.n = NextControl(stage_ctl)
 199
 200         # set up the input and output data
 201         if stage is not None:
 202             self._new_data("data")
 203
 204     def _new_data(self, name):
 205         """ allocates new data_i and data_o
 206         """
 207         self.p.data_i, self.n.data_o = self.new_specs(name)
 208
 209     @property
 210     def data_r(self):
 211         return self.process(self.p.data_i)
 212
 213     def connect_to_next(self, nxt):
 214         """ helper function to connect to the next stage data/valid/ready.
 215         """
 216         return self.n.connect_to_next(nxt.p)
 217
 218     def _connect_in(self, prev):
 219         """ internal helper function to connect stage to an input source.
 220             do not use to connect stage-to-stage!
 221         """
 222         return self.p._connect_in(prev.p)
 223
 224     def _connect_out(self, nxt):
 225         """ internal helper function to connect stage to an output source.
 226             do not use to connect stage-to-stage!
 227         """
 228         return self.n._connect_out(nxt.n)
 229
 230     def connect(self, pipechain):
 231         """ connects a chain (list) of Pipeline instances together and
 232             links them to this ControlBase instance:
 233
 234                       in <----> self <---> out
 235                        |                   ^
 236                        v                   |
 237                     [pipe1, pipe2, pipe3, pipe4]
 238                        |    ^  |    ^  |     ^
 239                        v    |  v    |  v     |
 240                      out---in out--in out---in
 241
 242             Also takes care of allocating data_i/data_o, by looking up
 243             the data spec for each end of the pipechain.  i.e It is NOT
 244             necessary to allocate self.p.data_i or self.n.data_o manually:
 245             this is handled AUTOMATICALLY, here.
 246
 247             Basically this function is the direct equivalent of StageChain,
 248             except that unlike StageChain, the Pipeline logic is followed.
 249
 250             Just as StageChain presents an object that conforms to the
 251             Stage API from a list of objects that also conform to the
 252             Stage API, an object that calls this Pipeline connect function
 253             has the exact same pipeline API as the list of pipline objects
 254             it is called with.
 255
 256             Thus it becomes possible to build up larger chains recursively.
 257             More complex chains (multi-input, multi-output) will have to be
 258             done manually.
 259
 260             Argument:
 261
 262             * :pipechain: - a sequence of ControlBase-derived classes
 263                             (must be one or more in length)
 264
 265             Returns:
 266
 267             * a list of eq assignments that will need to be added in
 268               an elaborate() to m.d.comb
 269         """
 270         assert len(pipechain) > 0, "pipechain must be non-zero length"
 271         assert self.stage is None, "do not use connect with a stage"
 272         eqs = [] # collated list of assignment statements
 273
 274         # connect inter-chain
 275         for i in range(len(pipechain)-1):
 276             pipe1 = pipechain[i]                # earlier
 277             pipe2 = pipechain[i+1]              # later (by 1)
 278             eqs += pipe1.connect_to_next(pipe2) # earlier n to later p
 279
 280         # connect front and back of chain to ourselves
 281         front = pipechain[0]                # first in chain
 282         end = pipechain[-1]                 # last in chain
 283         self.set_specs(front, end) # sets up ispec/ospec functions
 284         self._new_data("chain") # NOTE: REPLACES existing data
 285         eqs += front._connect_in(self)      # front p to our p
 286         eqs += end._connect_out(self)       # end n   to our n
 287
 288         return eqs
 289
 290     def set_input(self, i):
 291         """ helper function to set the input data (used in unit tests)
 292         """
 293         return nmoperator.eq(self.p.data_i, i)
 294
 295     def __iter__(self):
 296         yield from self.p # yields ready/valid/data (data also gets yielded)
 297         yield from self.n # ditto
 298
 299     def ports(self):
 300         return list(self)
 301
 302     def elaborate(self, platform):
 303         """ handles case where stage has dynamic ready/valid functions
 304         """
 305         m = Module()
 306         m.submodules.p = self.p
 307         m.submodules.n = self.n
 308
 309         self.setup(m, self.p.data_i)
 310
 311         if not self.p.stage_ctl:
 312             return m
 313
 314         # intercept the previous (outgoing) "ready", combine with stage ready
 315         m.d.comb += self.p.s_ready_o.eq(self.p._ready_o & self.stage.d_ready)
 316
 317         # intercept the next (incoming) "ready" and combine it with data valid
 318         sdv = self.stage.d_valid(self.n.ready_i)
 319         m.d.comb += self.n.d_valid.eq(self.n.ready_i & sdv)
 320
 321         return m
 322
 323
 324 class BufferedHandshake(ControlBase):
 325     """ buffered pipeline stage.  data and strobe signals travel in sync.
 326         if ever the input is ready and the output is not, processed data
 327         is shunted in a temporary register.
 328
 329         Argument: stage.  see Stage API above
 330
 331         stage-1   p.valid_i >>in   stage   n.valid_o out>>   stage+1
 332         stage-1   p.ready_o <<out  stage   n.ready_i <<in    stage+1
 333         stage-1   p.data_i  >>in   stage   n.data_o  out>>   stage+1
 334                               |             |
 335                             process --->----^
 336                               |             |
 337                               +-- r_data ->-+
 338
 339         input data p.data_i is read (only), is processed and goes into an
 340         intermediate result store [process()].  this is updated combinatorially.
 341
 342         in a non-stall condition, the intermediate result will go into the
 343         output (update_output).  however if ever there is a stall, it goes
 344         into r_data instead [update_buffer()].
 345
 346         when the non-stall condition is released, r_data is the first
 347         to be transferred to the output [flush_buffer()], and the stall
 348         condition cleared.
 349
 350         on the next cycle (as long as stall is not raised again) the
 351         input may begin to be processed and transferred directly to output.
 352     """
 353
 354     def elaborate(self, platform):
 355         self.m = ControlBase.elaborate(self, platform)
 356
 357         result = _spec(self.stage.ospec, "r_tmp")
 358         r_data = _spec(self.stage.ospec, "r_data")
 359
 360         # establish some combinatorial temporaries
 361         o_n_validn = Signal(reset_less=True)
 362         n_ready_i = Signal(reset_less=True, name="n_i_rdy_data")
 363         nir_por = Signal(reset_less=True)
 364         nir_por_n = Signal(reset_less=True)
 365         p_valid_i = Signal(reset_less=True)
 366         nir_novn = Signal(reset_less=True)
 367         nirn_novn = Signal(reset_less=True)
 368         por_pivn = Signal(reset_less=True)
 369         npnn = Signal(reset_less=True)
 370         self.m.d.comb += [p_valid_i.eq(self.p.valid_i_test),
 371                      o_n_validn.eq(~self.n.valid_o),
 372                      n_ready_i.eq(self.n.ready_i_test),
 373                      nir_por.eq(n_ready_i & self.p._ready_o),
 374                      nir_por_n.eq(n_ready_i & ~self.p._ready_o),
 375                      nir_novn.eq(n_ready_i | o_n_validn),
 376                      nirn_novn.eq(~n_ready_i & o_n_validn),
 377                      npnn.eq(nir_por | nirn_novn),
 378                      por_pivn.eq(self.p._ready_o & ~p_valid_i)
 379         ]
 380
 381         # store result of processing in combinatorial temporary
 382         self.m.d.comb += nmoperator.eq(result, self.data_r)
 383
 384         # if not in stall condition, update the temporary register
 385         with self.m.If(self.p.ready_o): # not stalled
 386             self.m.d.sync += nmoperator.eq(r_data, result) # update buffer
 387
 388         # data pass-through conditions
 389         with self.m.If(npnn):
 390             data_o = self._postprocess(result) # XXX TBD, does nothing right now
 391             self.m.d.sync += [self.n.valid_o.eq(p_valid_i), # valid if p_valid
 392                               nmoperator.eq(self.n.data_o, data_o), # update out
 393                              ]
 394         # buffer flush conditions (NOTE: can override data passthru conditions)
 395         with self.m.If(nir_por_n): # not stalled
 396             # Flush the [already processed] buffer to the output port.
 397             data_o = self._postprocess(r_data) # XXX TBD, does nothing right now
 398             self.m.d.sync += [self.n.valid_o.eq(1),  # reg empty
 399                               nmoperator.eq(self.n.data_o, data_o), # flush
 400                              ]
 401         # output ready conditions
 402         self.m.d.sync += self.p._ready_o.eq(nir_novn | por_pivn)
 403
 404         return self.m
 405
 406
 407 class MaskCancellable(ControlBase):
 408     """ Mask-activated Cancellable pipeline
 409
 410         Argument: stage.  see Stage API above
 411
 412         stage-1   p.valid_i >>in   stage   n.valid_o out>>   stage+1
 413         stage-1   p.ready_o <<out  stage   n.ready_i <<in    stage+1
 414         stage-1   p.data_i  >>in   stage   n.data_o  out>>   stage+1
 415                               |             |
 416                               +--process->--^
 417     """
 418
 419     def elaborate(self, platform):
 420         self.m = m = ControlBase.elaborate(self, platform)
 421
 422         # store result of processing in combinatorial temporary
 423         result = _spec(self.stage.ospec, "r_tmp")
 424         m.d.comb += nmoperator.eq(result, self.data_r)
 425
 426         # establish if the data should be passed on.  cancellation is
 427         # a global signal.
 428         # XXX EXCEPTIONAL CIRCUMSTANCES: inspection of the data payload
 429         # is NOT "normal" for the Stage API.
 430         p_valid_i = Signal(reset_less=True)
 431         m.d.comb += p_valid_i.eq((self.p.data_i.ctx.idmask & \
 432                                  ~self.cancelmask).bool()) # nonzero
 433
 434         # if idmask nonzero, data gets passed on.
 435         m.d.sync += self.n.valid_o.eq(p_valid_i)
 436         with m.If(p_valid_i):
 437             data_o = self._postprocess(result) # XXX TBD, does nothing right now
 438             m.d.sync += nmoperator.eq(self.n.data_o, data_o) # update output
 439
 440         # output valid if
 441         # input always "ready"
 442         m.d.comb += self.p._ready_o.eq(1)
 443
 444         return self.m
 445
 446
 447 class SimpleHandshake(ControlBase):
 448     """ simple handshake control.  data and strobe signals travel in sync.
 449         implements the protocol used by Wishbone and AXI4.
 450
 451         Argument: stage.  see Stage API above
 452
 453         stage-1   p.valid_i >>in   stage   n.valid_o out>>   stage+1
 454         stage-1   p.ready_o <<out  stage   n.ready_i <<in    stage+1
 455         stage-1   p.data_i  >>in   stage   n.data_o  out>>   stage+1
 456                               |             |
 457                               +--process->--^
 458         Truth Table
 459
 460         Inputs   Temporary  Output Data
 461         -------  ---------- -----  ----
 462         P P N N  PiV& ~NiR&  N P
 463         i o i o  PoR  NoV    o o
 464         V R R V              V R
 465
 466         -------   -    -     - -
 467         0 0 0 0   0    0    >0 0    reg
 468         0 0 0 1   0    1    >1 0    reg
 469         0 0 1 0   0    0     0 1    process(data_i)
 470         0 0 1 1   0    0     0 1    process(data_i)
 471         -------   -    -     - -
 472         0 1 0 0   0    0    >0 0    reg
 473         0 1 0 1   0    1    >1 0    reg
 474         0 1 1 0   0    0     0 1    process(data_i)
 475         0 1 1 1   0    0     0 1    process(data_i)
 476         -------   -    -     - -
 477         1 0 0 0   0    0    >0 0    reg
 478         1 0 0 1   0    1    >1 0    reg
 479         1 0 1 0   0    0     0 1    process(data_i)
 480         1 0 1 1   0    0     0 1    process(data_i)
 481         -------   -    -     - -
 482         1 1 0 0   1    0     1 0    process(data_i)
 483         1 1 0 1   1    1     1 0    process(data_i)
 484         1 1 1 0   1    0     1 1    process(data_i)
 485         1 1 1 1   1    0     1 1    process(data_i)
 486         -------   -    -     - -
 487     """
 488
 489     def elaborate(self, platform):
 490         self.m = m = ControlBase.elaborate(self, platform)
 491
 492         r_busy = Signal()
 493         result = _spec(self.stage.ospec, "r_tmp")
 494
 495         # establish some combinatorial temporaries
 496         n_ready_i = Signal(reset_less=True, name="n_i_rdy_data")
 497         p_valid_i_p_ready_o = Signal(reset_less=True)
 498         p_valid_i = Signal(reset_less=True)
 499         m.d.comb += [p_valid_i.eq(self.p.valid_i_test),
 500                      n_ready_i.eq(self.n.ready_i_test),
 501                      p_valid_i_p_ready_o.eq(p_valid_i & self.p.ready_o),
 502         ]
 503
 504         # store result of processing in combinatorial temporary
 505         m.d.comb += nmoperator.eq(result, self.data_r)
 506
 507         # previous valid and ready
 508         with m.If(p_valid_i_p_ready_o):
 509             data_o = self._postprocess(result) # XXX TBD, does nothing right now
 510             m.d.sync += [r_busy.eq(1),      # output valid
 511                          nmoperator.eq(self.n.data_o, data_o), # update output
 512                         ]
 513         # previous invalid or not ready, however next is accepting
 514         with m.Elif(n_ready_i):
 515             data_o = self._postprocess(result) # XXX TBD, does nothing right now
 516             m.d.sync += [nmoperator.eq(self.n.data_o, data_o)]
 517             # TODO: could still send data here (if there was any)
 518             #m.d.sync += self.n.valid_o.eq(0) # ...so set output invalid
 519             m.d.sync += r_busy.eq(0) # ...so set output invalid
 520
 521         m.d.comb += self.n.valid_o.eq(r_busy)
 522         # if next is ready, so is previous
 523         m.d.comb += self.p._ready_o.eq(n_ready_i)
 524
 525         return self.m
 526
 527
 528 class UnbufferedPipeline(ControlBase):
 529     """ A simple pipeline stage with single-clock synchronisation
 530         and two-way valid/ready synchronised signalling.
 531
 532         Note that a stall in one stage will result in the entire pipeline
 533         chain stalling.
 534
 535         Also that unlike BufferedHandshake, the valid/ready signalling does NOT
 536         travel synchronously with the data: the valid/ready signalling
 537         combines in a *combinatorial* fashion.  Therefore, a long pipeline
 538         chain will lengthen propagation delays.
 539
 540         Argument: stage.  see Stage API, above
 541
 542         stage-1   p.valid_i >>in   stage   n.valid_o out>>   stage+1
 543         stage-1   p.ready_o <<out  stage   n.ready_i <<in    stage+1
 544         stage-1   p.data_i  >>in   stage   n.data_o  out>>   stage+1
 545                               |             |
 546                             r_data        result
 547                               |             |
 548                               +--process ->-+
 549
 550         Attributes:
 551         -----------
 552         p.data_i : StageInput, shaped according to ispec
 553             The pipeline input
 554         p.data_o : StageOutput, shaped according to ospec
 555             The pipeline output
 556         r_data : input_shape according to ispec
 557             A temporary (buffered) copy of a prior (valid) input.
 558             This is HELD if the output is not ready.  It is updated
 559             SYNCHRONOUSLY.
 560         result: output_shape according to ospec
 561             The output of the combinatorial logic.  it is updated
 562             COMBINATORIALLY (no clock dependence).
 563
 564         Truth Table
 565
 566         Inputs  Temp  Output  Data
 567         -------   -   -----   ----
 568         P P N N ~NiR&  N P
 569         i o i o  NoV   o o
 570         V R R V        V R
 571
 572         -------   -    - -
 573         0 0 0 0   0    0 1    reg
 574         0 0 0 1   1    1 0    reg
 575         0 0 1 0   0    0 1    reg
 576         0 0 1 1   0    0 1    reg
 577         -------   -    - -
 578         0 1 0 0   0    0 1    reg
 579         0 1 0 1   1    1 0    reg
 580         0 1 1 0   0    0 1    reg
 581         0 1 1 1   0    0 1    reg
 582         -------   -    - -
 583         1 0 0 0   0    1 1    reg
 584         1 0 0 1   1    1 0    reg
 585         1 0 1 0   0    1 1    reg
 586         1 0 1 1   0    1 1    reg
 587         -------   -    - -
 588         1 1 0 0   0    1 1    process(data_i)
 589         1 1 0 1   1    1 0    process(data_i)
 590         1 1 1 0   0    1 1    process(data_i)
 591         1 1 1 1   0    1 1    process(data_i)
 592         -------   -    - -
 593
 594         Note: PoR is *NOT* involved in the above decision-making.
 595     """
 596
 597     def elaborate(self, platform):
 598         self.m = m = ControlBase.elaborate(self, platform)
 599
 600         data_valid = Signal() # is data valid or not
 601         r_data = _spec(self.stage.ospec, "r_tmp") # output type
 602
 603         # some temporaries
 604         p_valid_i = Signal(reset_less=True)
 605         pv = Signal(reset_less=True)
 606         buf_full = Signal(reset_less=True)
 607         m.d.comb += p_valid_i.eq(self.p.valid_i_test)
 608         m.d.comb += pv.eq(self.p.valid_i & self.p.ready_o)
 609         m.d.comb += buf_full.eq(~self.n.ready_i_test & data_valid)
 610
 611         m.d.comb += self.n.valid_o.eq(data_valid)
 612         m.d.comb += self.p._ready_o.eq(~data_valid | self.n.ready_i_test)
 613         m.d.sync += data_valid.eq(p_valid_i | buf_full)
 614
 615         with m.If(pv):
 616             m.d.sync += nmoperator.eq(r_data, self.data_r)
 617         data_o = self._postprocess(r_data) # XXX TBD, does nothing right now
 618         m.d.comb += nmoperator.eq(self.n.data_o, data_o)
 619
 620         return self.m
 621
 622
 623 class UnbufferedPipeline2(ControlBase):
 624     """ A simple pipeline stage with single-clock synchronisation
 625         and two-way valid/ready synchronised signalling.
 626
 627         Note that a stall in one stage will result in the entire pipeline
 628         chain stalling.
 629
 630         Also that unlike BufferedHandshake, the valid/ready signalling does NOT
 631         travel synchronously with the data: the valid/ready signalling
 632         combines in a *combinatorial* fashion.  Therefore, a long pipeline
 633         chain will lengthen propagation delays.
 634
 635         Argument: stage.  see Stage API, above
 636
 637         stage-1   p.valid_i >>in   stage   n.valid_o out>>   stage+1
 638         stage-1   p.ready_o <<out  stage   n.ready_i <<in    stage+1
 639         stage-1   p.data_i  >>in   stage   n.data_o  out>>   stage+1
 640                               |             |    |
 641                               +- process-> buf <-+
 642         Attributes:
 643         -----------
 644         p.data_i : StageInput, shaped according to ispec
 645             The pipeline input
 646         p.data_o : StageOutput, shaped according to ospec
 647             The pipeline output
 648         buf : output_shape according to ospec
 649             A temporary (buffered) copy of a valid output
 650             This is HELD if the output is not ready.  It is updated
 651             SYNCHRONOUSLY.
 652
 653         Inputs  Temp  Output Data
 654         -------   -   -----
 655         P P N N ~NiR&  N P   (buf_full)
 656         i o i o  NoV   o o
 657         V R R V        V R
 658
 659         -------   -    - -
 660         0 0 0 0   0    0 1   process(data_i)
 661         0 0 0 1   1    1 0   reg (odata, unchanged)
 662         0 0 1 0   0    0 1   process(data_i)
 663         0 0 1 1   0    0 1   process(data_i)
 664         -------   -    - -
 665         0 1 0 0   0    0 1   process(data_i)
 666         0 1 0 1   1    1 0   reg (odata, unchanged)
 667         0 1 1 0   0    0 1   process(data_i)
 668         0 1 1 1   0    0 1   process(data_i)
 669         -------   -    - -
 670         1 0 0 0   0    1 1   process(data_i)
 671         1 0 0 1   1    1 0   reg (odata, unchanged)
 672         1 0 1 0   0    1 1   process(data_i)
 673         1 0 1 1   0    1 1   process(data_i)
 674         -------   -    - -
 675         1 1 0 0   0    1 1   process(data_i)
 676         1 1 0 1   1    1 0   reg (odata, unchanged)
 677         1 1 1 0   0    1 1   process(data_i)
 678         1 1 1 1   0    1 1   process(data_i)
 679         -------   -    - -
 680
 681         Note: PoR is *NOT* involved in the above decision-making.
 682     """
 683
 684     def elaborate(self, platform):
 685         self.m = m = ControlBase.elaborate(self, platform)
 686
 687         buf_full = Signal() # is data valid or not
 688         buf = _spec(self.stage.ospec, "r_tmp") # output type
 689
 690         # some temporaries
 691         p_valid_i = Signal(reset_less=True)
 692         m.d.comb += p_valid_i.eq(self.p.valid_i_test)
 693
 694         m.d.comb += self.n.valid_o.eq(buf_full | p_valid_i)
 695         m.d.comb += self.p._ready_o.eq(~buf_full)
 696         m.d.sync += buf_full.eq(~self.n.ready_i_test & self.n.valid_o)
 697
 698         data_o = Mux(buf_full, buf, self.data_r)
 699         data_o = self._postprocess(data_o) # XXX TBD, does nothing right now
 700         m.d.comb += nmoperator.eq(self.n.data_o, data_o)
 701         m.d.sync += nmoperator.eq(buf, self.n.data_o)
 702
 703         return self.m
 704
 705
 706 class PassThroughHandshake(ControlBase):
 707     """ A control block that delays by one clock cycle.
 708
 709         Inputs   Temporary          Output Data
 710         -------  ------------------  ----- ----
 711         P P N N  PiV& PiV| NiR| pvr   N P  (pvr)
 712         i o i o  PoR  ~PoR ~NoV       o o
 713         V R R V                       V R
 714
 715         -------   -    -    -   -     - -
 716         0 0 0 0   0    1    1   0     1 1   odata (unchanged)
 717         0 0 0 1   0    1    0   0     1 0   odata (unchanged)
 718         0 0 1 0   0    1    1   0     1 1   odata (unchanged)
 719         0 0 1 1   0    1    1   0     1 1   odata (unchanged)
 720         -------   -    -    -   -     - -
 721         0 1 0 0   0    0    1   0     0 1   odata (unchanged)
 722         0 1 0 1   0    0    0   0     0 0   odata (unchanged)
 723         0 1 1 0   0    0    1   0     0 1   odata (unchanged)
 724         0 1 1 1   0    0    1   0     0 1   odata (unchanged)
 725         -------   -    -    -   -     - -
 726         1 0 0 0   0    1    1   1     1 1   process(in)
 727         1 0 0 1   0    1    0   0     1 0   odata (unchanged)
 728         1 0 1 0   0    1    1   1     1 1   process(in)
 729         1 0 1 1   0    1    1   1     1 1   process(in)
 730         -------   -    -    -   -     - -
 731         1 1 0 0   1    1    1   1     1 1   process(in)
 732         1 1 0 1   1    1    0   0     1 0   odata (unchanged)
 733         1 1 1 0   1    1    1   1     1 1   process(in)
 734         1 1 1 1   1    1    1   1     1 1   process(in)
 735         -------   -    -    -   -     - -
 736
 737     """
 738
 739     def elaborate(self, platform):
 740         self.m = m = ControlBase.elaborate(self, platform)
 741
 742         r_data = _spec(self.stage.ospec, "r_tmp") # output type
 743
 744         # temporaries
 745         p_valid_i = Signal(reset_less=True)
 746         pvr = Signal(reset_less=True)
 747         m.d.comb += p_valid_i.eq(self.p.valid_i_test)
 748         m.d.comb += pvr.eq(p_valid_i & self.p.ready_o)
 749
 750         m.d.comb += self.p.ready_o.eq(~self.n.valid_o |  self.n.ready_i_test)
 751         m.d.sync += self.n.valid_o.eq(p_valid_i       | ~self.p.ready_o)
 752
 753         odata = Mux(pvr, self.data_r, r_data)
 754         m.d.sync += nmoperator.eq(r_data, odata)
 755         r_data = self._postprocess(r_data) # XXX TBD, does nothing right now
 756         m.d.comb += nmoperator.eq(self.n.data_o, r_data)
 757
 758         return m
 759
 760
 761 class RegisterPipeline(UnbufferedPipeline):
 762     """ A pipeline stage that delays by one clock cycle, creating a
 763         sync'd latch out of data_o and valid_o as an indirect byproduct
 764         of using PassThroughStage
 765     """
 766     def __init__(self, iospecfn):
 767         UnbufferedPipeline.__init__(self, PassThroughStage(iospecfn))
 768
 769
 770 class FIFOControl(ControlBase):
 771     """ FIFO Control.  Uses Queue to store data, coincidentally
 772         happens to have same valid/ready signalling as Stage API.
 773
 774         data_i -> fifo.din -> FIFO -> fifo.dout -> data_o
 775     """
 776     def __init__(self, depth, stage, in_multi=None, stage_ctl=False,
 777                                      fwft=True, pipe=False):
 778         """ FIFO Control
 779
 780             * :depth: number of entries in the FIFO
 781             * :stage: data processing block
 782             * :fwft:  first word fall-thru mode (non-fwft introduces delay)
 783             * :pipe:  specifies pipe mode.
 784
 785             when fwft = True it indicates that transfers may occur
 786             combinatorially through stage processing in the same clock cycle.
 787             This requires that the Stage be a Moore FSM:
 788             https://en.wikipedia.org/wiki/Moore_machine
 789
 790             when fwft = False it indicates that all output signals are
 791             produced only from internal registers or memory, i.e. that the
 792             Stage is a Mealy FSM:
 793             https://en.wikipedia.org/wiki/Mealy_machine
 794
 795             data is processed (and located) as follows:
 796
 797             self.p  self.stage temp    fn temp  fn  temp  fp   self.n
 798             data_i->process()->result->cat->din.FIFO.dout->cat(data_o)
 799
 800             yes, really: cat produces a Cat() which can be assigned to.
 801             this is how the FIFO gets de-catted without needing a de-cat
 802             function
 803         """
 804         self.fwft = fwft
 805         self.pipe = pipe
 806         self.fdepth = depth
 807         ControlBase.__init__(self, stage, in_multi, stage_ctl)
 808
 809     def elaborate(self, platform):
 810         self.m = m = ControlBase.elaborate(self, platform)
 811
 812         # make a FIFO with a signal of equal width to the data_o.
 813         (fwidth, _) = nmoperator.shape(self.n.data_o)
 814         fifo = Queue(fwidth, self.fdepth, fwft=self.fwft, pipe=self.pipe)
 815         m.submodules.fifo = fifo
 816
 817         def processfn(data_i):
 818             # store result of processing in combinatorial temporary
 819             result = _spec(self.stage.ospec, "r_temp")
 820             m.d.comb += nmoperator.eq(result, self.process(data_i))
 821             return nmoperator.cat(result)
 822
 823         ## prev: make the FIFO (Queue object) "look" like a PrevControl...
 824         m.submodules.fp = fp = PrevControl()
 825         fp.valid_i, fp._ready_o, fp.data_i = fifo.we, fifo.writable, fifo.din
 826         m.d.comb += fp._connect_in(self.p, fn=processfn)
 827
 828         # next: make the FIFO (Queue object) "look" like a NextControl...
 829         m.submodules.fn = fn = NextControl()
 830         fn.valid_o, fn.ready_i, fn.data_o  = fifo.readable, fifo.re, fifo.dout
 831         connections = fn._connect_out(self.n, fn=nmoperator.cat)
 832
 833         # ok ok so we can't just do the ready/valid eqs straight:
 834         # first 2 from connections are the ready/valid, 3rd is data.
 835         if self.fwft:
 836             m.d.comb += connections[:2] # combinatorial on next ready/valid
 837         else:
 838             m.d.sync += connections[:2]  # non-fwft mode needs sync
 839         data_o = connections[2] # get the data
 840         data_o = self._postprocess(data_o) # XXX TBD, does nothing right now
 841         m.d.comb += data_o
 842
 843         return m
 844
 845
 846 # aka "RegStage".
 847 class UnbufferedPipeline(FIFOControl):
 848     def __init__(self, stage, in_multi=None, stage_ctl=False):
 849         FIFOControl.__init__(self, 1, stage, in_multi, stage_ctl,
 850                                    fwft=True, pipe=False)
 851
 852 # aka "BreakReadyStage" XXX had to set fwft=True to get it to work
 853 class PassThroughHandshake(FIFOControl):
 854     def __init__(self, stage, in_multi=None, stage_ctl=False):
 855         FIFOControl.__init__(self, 1, stage, in_multi, stage_ctl,
 856                                    fwft=True, pipe=True)
 857
 858 # this is *probably* BufferedHandshake, although test #997 now succeeds.
 859 class BufferedHandshake(FIFOControl):
 860     def __init__(self, stage, in_multi=None, stage_ctl=False):
 861         FIFOControl.__init__(self, 2, stage, in_multi, stage_ctl,
 862                                    fwft=True, pipe=False)
 863
 864
 865 """
 866 # this is *probably* SimpleHandshake (note: memory cell size=0)
 867 class SimpleHandshake(FIFOControl):
 868     def __init__(self, stage, in_multi=None, stage_ctl=False):
 869         FIFOControl.__init__(self, 0, stage, in_multi, stage_ctl,
 870                                    fwft=True, pipe=False)
 871 """