3d_gpu.mdwn

   1 # RISC-V 3D GPU / CPU / VPU
   2
   3 Note: this is a **hybrid** CPU, VPU and GPU.  It is not, as many news articles
   4 are implying, a "dedicated exclusive GPU".  The option exists to **create**
   5 a stand-alone GPU product (contact us if this is a product that you want).
   6 Our primary goal is to design a **complete** all-in-one processor
   7 (System-on-a-Chip) that happens to include a libre-licensed VPU and GPU.
   8
   9 We seek investors, sponsors (whose contributions thanks to NLNet may be tax-deductible), engineers and potential customers, who are
  10 interested, as a first product, in the creation and use of an entirely
  11 libre low-power mobile class system-on-a-chip.  Comparative benchmark
  12 performance, pincount and price is the Allwinner A64, except that the
  13 power budget target is 2.5 watts in a 16x16mm 320 to 360 pin 0.8mm
  14 FBGA package.  Instead of single-issue higher clock rate, the design is
  15 multi-issue, aiming for around 800mhz.
  16
  17 The lower pincount, lower power, and higher BGA pitch is all to reduce
  18 the cost of product development when it comes to PCB design and layout:
  19
  20 * Above 4 watts requires metal packages, greater attention to thermal
  21   management in the PCB design and layout, and much pricier PMICs.
  22 * 0.6mm pitch BGA and below requires much more expensive PCB manufacturing
  23   equipment and more costly PCBA techniques.
  24 * Above 600 pins begins to reduce production yields as well as increase
  25   the cost of testing and packaging.
  26
  27 We can look at larger higher-power ASICs either later or, if funding
  28 is made available, immediately.
  29
  30 Recent applications to NLNet (Oct 2019) are for a test chip in 180nm, 64 bit, single core dual issue, around 300 to 350mhz.  This will provide the confidence to go to higher geometries, as well as be a commercially viable embedded product in its own right.
  31
  32 # Business Objectives
  33
  34 * the project shall be a hybrid CPU-GPU
  35 * the project shall be commercial and mass-volume (100 million units
  36   and above)
  37 * the project shall be entirely transparent so that end-users will be
  38   able to trust it
  39 * the source code shall be available at all times for all components
  40   for BUSINESS reasons, making development and use of SDKs dead simple
  41   and aiding and assisting developers AND BUSINESSES in debugging and thus
  42   hugely saving them money.
  43
  44 Reasoning:
  45
  46 * If the processor is not a hybrid CPU-GPU-VPU, the
  47   complexity involved in developing a split shared-memory CPU-GPU both
  48   at a hardware and a software level will be so costly it will jeapordise
  49   the project.
  50 * The project is commercial and mass-volume because there are plenty
  51   of academic designs (none of them reaching production where people
  52   may benefit), and "Open" designs, created by the Open Hardware
  53   Community, sadly due to the high cost of producing ASICs, tend to be
  54   focussed on markets that would have been great about twenty to thirty
  55   years ago.
  56 * Transparency is a key business objective.  It is a Unique Selling Point
  57   that the processor is developed in a fashion that, should it be
  58   independently audited, no opportunity for spying back-door co-processors
  59   will be found to have "made their way surreptitiously - or overtly -
  60   into the design".  Yes, GCHQ: I know about the conversation you had
  61   with nCipher (and, to their everlasting credit, that they told you
  62   to take a hike)
  63
  64 # Links:
  65
  66 * [[shakti/m_class/libre_3d_gpu]]
  67 * [[discussion]]
  68 * [[resources]]
  69 * [[overview]]
  70 * [[3d_gpu/funding]]
  71 * [[3d_gpu/architecture]]
  72 * Founding [[charter]]
  73 * Mailing list <http://lists.libre-riscv.org/pipermail/libre-riscv-dev/>
  74 * Crowdsupply page <https://www.crowdsupply.com/libre-risc-v/m-class>
  75 * Wiki <https://libre-riscv.org>
  76 * Git repositories <https://git.libre-riscv.org>
  77 * Bugtracker <http://bugs.libre-riscv.org>
  78 * Kazan Vulkan Driver (including 3D engine) <https://salsa.debian.org/Kazan-team/kazan>
  79 * [NLNet 2019 Milestones](http://bugs.libre-riscv.org/buglist.cgi?columnlist=assigned_to%2Cbug_status%2Cresolution%2Cshort_desc%2Ccf_budget&f1=cf_nlnet_milestone&o1=equals&query_format=advanced&resolution=---&v1=NLnet.2019.02)
  80 * NLNet Project Page <https://nlnet.nl/project/Libre-RISCV/>
  81 * [[nlnet_proposals]]
  82
  83 # Progress:
  84
  85 * Dec 2019: Second round NLNet questions answered.  External Review completed.  6 NLNet proposals accepted (EUR 200,000+)
  86 * Nov 2019: Alternative FP library to Berkeley softfloat developed. NLNet first round questions answered.
  87 * Oct 2019: 3D Standards continued.  POWER ISA considered.  Open 3D Alliance begins.  NLNet funding applications submitted.
  88 * Sep 2019: 3D Standards continued.  Additional NLNet Funding proposals discussed.
  89 * Aug 2019: Development of "Transcendentals" (SIN/COS/ATAN2) Specifications
  90 * Jul 2019: Sponsorship from Purism received.  IEEE754 FP Mul, Add, DIV,
  91   FCLASS and FCVT pipelines completed.
  92 * Jun 2019: IEEE754 FP Mul, Add, and FSM "DIV" completed.
  93 * May 2019: 6600-style scoreboard started
  94 * Apr 2019: NLnet funding approved by independent review committee
  95 * Mar 2019: NLnet funding application first and second phase passed
  96 * Mar 2019: First successful nmigen pipeline milestone achieved with IEEE754 FADD
  97 * Feb 2019: Conversion of John Dawson's IEEE754 FPU to nmigen started
  98 * Jan 2019: Second version Simple-V preliminary proposal (suited to LLVM)
  99 * 2017 - Nov 2018: Simple-V specification preliminary draft completed
 100 * Aug 2018 - Nov 2018: spike-sv implementation of draft spec completed
 101 * Aug 2018: Kazan Vulkan Driver initiated
 102 * Sep 2018: mailing list established
 103 * Sep 2018: Crowdsupply pre-launch page up (for updates)
 104 * Dec 2018: preliminary floorplan and architecture designed (comp.arch)
 105
 106 # News Articles
 107
 108 * <https://www.phoronix.com/forums/forum/hardware/processors-memory/1133806-libre-risc-v-open-source-effort-now-looking-at-power-instead-of-risc-v/page7>
 109 * <https://hub.packtpub.com/a-libre-gpu-effort-based-on-risc-v-rust-llvm-and-vulkan-by-the-developer-of-an-earth-friendly-computer/>
 110 * <https://riscv.org/2018/10/packt-hub-article-a-libre-gpu-effort-based-on-risc-v-rust-llvm-and-vulkan-by-the-developer-of-an-earth-friendly-computer/>
 111 * <https://www.reddit.com/r/RISCV/comments/9jts9t/theres_a_new_libre_gpu_effort_building_on_riscv/>
 112 * <https://www.linux.com/blog/2018/11/risc-v-linux-development-full-swing>
 113 * <https://www.phoronix.com/scan.php?page=news_item&px=Libre-GPU-RISC-V-Vulkan>
 114 * <https://www.heise.de/newsticker/meldung/Mobilprozessor-mit-freier-GPU-Libre-RISC-V-M-Class-geplant-4242802.html>
 115 * <https://news.ycombinator.com/item?id=18094734>
 116 * <http://www.tuxmachines.org/node/116004>
 117 * <https://linuxfr.org/users/martoni/journaux/risc-v-est-pret-pour-le-desktop>
 118 * <https://www.reddit.com/r/hardware/comments/9jlby1/theres_a_new_libre_gpu_effort_building_on_riscv/>
 119 * <http://www.eevblog.com/forum/crowd-funded-projects/libre-risc-v-m-class-with-open-source-gpu-and-kazan-vulkan-driver/>
 120 * <https://www.reddit.com/domain/libre-riscv.org/>
 121 * <https://hardware.slashdot.org/comments.pl?sid=13447940&cid=58160868>
 122 * <https://www.phoronix.com/forums/forum/hardware/graphics-cards/1080755-libre-risc-v-gpu-aiming-for-2-5-watt-power-draw-continues-being-plotted/page5>
 123 * <https://www.phoronix.com/forums/forum/hardware/processors-memory/1070828-more-details-on-the-proposed-simple-v-extension-to-risc-v-for-gpu-workloads>
 124 * <https://slashdot.org/submission/9750302/nlnet-funds-development-of-a-libre-risc-v-3d-cpu>
 125 * <https://hardware.slashdot.org/story/19/06/02/0153243/nlnet-funds-development-of-a-libre-risc-v-3d-cpu>
 126 * <https://www.phoronix.com/forums/forum/hardware/graphics-cards/1104124-libre-risc-v-snags-50k-eur-grant-to-work-on-its-risc-v-3d-gpu-chip/page6>
 127 * <https://news.ycombinator.com/item?id=21112341>
 128 * <https://www.reddit.com/r/RISCV/comments/db04j3/libreriscv_3d_cpugpu_seeks_grants_for_ambitious/>
 129 * <https://hardware.slashdot.org/story/19/09/29/1845252/libre-risc-v-3d-cpugpu-seeks-grants-for-ambitious-expansion>
 130 * <https://forums.puri.sm/t/risc-v-m-class-effort-and-purism-donation/6528/15>
 131 * <https://www.pro-linux.de/news/1/27527/comm/1/show-all-comments.html>
 132
 133 # Information Resources and Tutorials
 134
 135 * <https://github.com/timvideos/litex-buildenv/wiki/LiteX-for-Hardware-Engineers>
 136 * <https://jeffrey.co.in/blog/2014/01/d-flip-flop-using-migen/>
 137 * <http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2019-March/000705.html>
 138 * <https://chisel.eecs.berkeley.edu/api/latest/chisel3/util/DecoupledIO.html>
 139 * <http://www.clifford.at/papers/2016/yosys-synth-formal/slides.pdf>
 140 * <http://blog.lambdaconcept.com/doku.php?id=migen:tutorial>
 141 * <http://chiselapp.com/user/kc5tja/repository/kestrel-3/dir?ci=6c559135a301f321&name=cores/cpu>
 142 * <https://chips4makers.io/blog/>
 143 * <https://hackaday.io/project/7817-zynqberry>
 144 * <https://wiki.f-si.org/index.php/FSiC2019>
 145 * <https://github.com/efabless/raven-picorv32> - <https://efabless.com>
 146 * <https://efabless.com/design_catalog/default>
 147 * <https://toyota-ai.ventures/>
 148 * <https://github.com/lambdaconcept/minerva>
 149 * <https://en.wikipedia.org/wiki/Liskov_substitution_principle>
 150 * <https://en.wikipedia.org/wiki/Principle_of_least_astonishment>
 151 * <https://peertube.f-si.org/videos/watch/379ef007-40b7-4a51-ba1a-0db4f48e8b16>
 152 * <https://github.com/riscv/riscv-sbi-doc/blob/master/riscv-sbi.md>
 153 * <https://mshahrad.github.io/openpiton-asplos16.html>
 154 * <https://wiki.f-si.org/index.php/The_Raven_chip:_First-time_silicon_success_with_qflow_and_efabless>
 155 * <http://smallcultfollowing.com/babysteps/blog/2019/04/19/aic-adventures-in-consensus/>
 156 * <http://www.crnhq.org/12-Skills-Summary.aspx?rw=c>
 157 * <http://bugs.libre-riscv.org/buglist.cgi?columnlist=assigned_to%2Cbug_status%2Cresolution%2Cshort_desc%2Ccf_budget&f1=cf_nlnet_milestone&o1=equals&query_format=advanced&resolution=---&v1=NLnet.2019.02>
 158 * <https://pdfs.semanticscholar.org/5060/4e9aff0e37089c4ab9a376c3f35761ffe28b.pdf>
 159 * <http://www.acsel-lab.com/arithmetic/arith15/papers/ARITH15_Takagi.pdf>
 160 * <https://youtu.be/o5Ihqg72T3c>
 161 * <http://flopoco.gforge.inria.fr/>
 162 * Fundamentals of Modern VLSI Devices <https://groups.google.com/a/groups.riscv.org/d/msg/hw-dev/b4pPvlzBzu0/7hDfxArEAgAJ>
 163
 164 # Analog Simulation
 165
 166 * <https://github.com/Isotel/mixedsim>
 167 * <http://www.vlsiacademy.org/open-source-cad-tools.html>
 168 * <http://ngspice.sourceforge.net/adms.html>
 169 * <https://en.wikipedia.org/wiki/Verilog-AMS#Open_Source_Implementations>
 170
 171 # Evaluations
 172
 173 *[[openpower]]