3d_gpu.mdwn

   1 See architectural details [here](./architecture)
   2
   3 # Hybrid 3D GPU / CPU / VPU
   4
   5 Creating a trustworthy processor for the world.
   6
   7 Our [[3d_gpu/business_objectives]]
   8
   9 Note: this is a **hybrid** CPU, VPU and GPU.  It is not, as many news articles
  10 are implying, a "dedicated exclusive GPU".  The option exists to *create*
  11 a stand-alone GPU product (contact us if this is a product that you want).
  12 Our primary goal is to design a **complete** all-in-one processor
  13 (System-on-a-Chip) that happens to include libre-licensed VPU and GPU
  14 accelerated instructions as part of the actual - main - CPU itself.  This greatly simplifies driver development, applications integration and debugging, reducing costs and time to market in the process.
  15
  16 We seek investors, sponsors (whose contributions thanks to NLNet may be
  17 tax-deductible), engineers and potential customers, who are
  18 interested, as a first product, in the creation and use of an entirely
  19 libre low-power mobile class system-on-a-chip.  Comparative benchmark
  20 performance, pincount and price is the Allwinner A64, except that the
  21 power budget target is 2.5 watts in a 16x16mm 320 to 360 pin 0.8mm
  22 FBGA package.  Instead of single-issue higher clock rate, the design is
  23 multi-issue, aiming for around 800mhz.
  24
  25 The lower pincount, lower power, and higher BGA pitch is all to reduce
  26 the cost of product development when it comes to PCB design and layout:
  27
  28 * Above 4 watts requires metal packages, greater attention to thermal
  29   management in the PCB design and layout, and much pricier PMICs.
  30 * 0.6mm pitch BGA and below requires much more expensive PCB manufacturing
  31   equipment and more costly PCBA techniques.
  32 * Above 600 pins begins to reduce production yields as well as increase
  33   the cost of testing and packaging.
  34
  35 We can look at larger higher-power ASICs either later or, if funding
  36 is made available, immediately.
  37
  38 Recent applications to NLNet (Oct 2019) are for a test chip in 180nm,
  39 64 bit, single core dual issue, around 300 to 350mhz.  This will provide
  40 the confidence to go to higher geometries, as well as be a commercially
  41 viable embedded product in its own right. Tapeout deadline is Oct 2020.
  42
  43 See [[3d_gpu/articles]] online.
  44
  45 # Progress:
  46
  47 * Sep 2020: [first boot](https://youtu.be/72QmWro9BSE) of Litex BIOS on a Versa ECP5 at 55mhz.  DDR3 RAM initialisation successful.
  48 * Aug 2020: [first boot](https://libre-soc.org/3d_gpu/libresoc_litex_bios_first_execution_2020-08-06_16-15.png) of litex BIOS in verilator simulation
  49 * Jul 2020: first ppc64le "hello world" binary executed.  80,000 gate coriolis2 auto-layout completed with 99.98% routing. Wishbone MoU signed making available access to an additional EUR 50,000 donations from NLNet. XDC2020 and OpenPOWER conference submissions entered.
  50 * Jun 2020: core unit tests and pipeline formal correctness proofs in place.
  51 * May 2020: first integer pipelines (ALU, Logical, Branch, Trap, SPR, ShiftRot, Mul, Div) and register files (XER, CR, INT, FAST, SPR) started.
  52 * Mar 2020: Coriolis2 Layout experiments successful. 6600 Memory Architecture
  53   exploration started.  OpenPOWER ISA decoder started.  Two new people:
  54   Alain and Jock.
  55 * Feb 2020: OpenPower Foundation EULA released. Coriolis2 Layout experimentation begun. Dynamic Partitioned SIMD ALU created.
  56 * Jan 2020: New team members, Yehowshua and Michael.  Last-minute attendance of FOSDEM2020
  57 * Dec 2019: Second round NLNet questions answered.  External Review completed.  6 NLNet proposals accepted (EUR 200,000+)
  58 * Nov 2019: Alternative FP library to Berkeley softfloat developed. NLNet first round questions answered.
  59 * Oct 2019: 3D Standards continued.  POWER ISA considered.  Open 3D Alliance begins.  NLNet funding applications submitted.
  60 * Sep 2019: 3D Standards continued.  Additional NLNet Funding proposals discussed.
  61 * Aug 2019: Development of "Transcendentals" (SIN/COS/ATAN2) Specifications
  62 * Jul 2019: Sponsorship from Purism received.  IEEE754 FP Mul, Add, DIV,
  63   FCLASS and FCVT pipelines completed.
  64 * Jun 2019: IEEE754 FP Mul, Add, and FSM "DIV" completed.
  65 * May 2019: 6600-style scoreboard started
  66 * Apr 2019: NLnet funding approved by independent review committee
  67 * Mar 2019: NLnet funding application first and second phase passed
  68 * Mar 2019: First successful nmigen pipeline milestone achieved with IEEE754 FADD
  69 * Feb 2019: Conversion of John Dawson's IEEE754 FPU to nmigen started
  70 * Jan 2019: Second version Simple-V preliminary proposal (suited to LLVM)
  71 * 2017 - Nov 2018: Simple-V specification preliminary draft completed
  72 * Aug 2018 - Nov 2018: spike-sv implementation of draft spec completed
  73 * Aug 2018: Kazan Vulkan Driver initiated
  74 * Sep 2018: mailing list established
  75 * Sep 2018: Crowdsupply pre-launch page up (for updates)
  76 * Dec 2018: preliminary floorplan and architecture designed (comp.arch)
  77
  78
  79 # Evaluations
  80
  81 * [[openpower]]
  82
  83 # Drivers
  84
  85 * [[3d_gpu/opencl]]
  86 * [[3d_gpu/mesa]]