3d_gpu.mdwn

   1 # RISC-V 3D GPU / CPU / VPU
   2
   3 Note: this is a **hybrid** CPU, VPU and GPU.  It is not, as many news articles
   4 are implying, a "dedicated exclusive GPU".  The option exists to **create**
   5 a stand-alone GPU product (contact us if this is a product that you want).
   6 Our primary goal is to design a **complete** all-in-one processor
   7 (System-on-a-Chip) that happens to include a libre-licensed VPU and GPU.
   8
   9 We seek investors, sponsors, engineers and potential customers, who are
  10 interested, as a first product, in the creation and use of an entirely
  11 libre low-power mobile class system-on-a-chip.  Comparative benchmark
  12 performance, pincount and price is the Allwinner A64, except that the
  13 power budget target is 2.5 watts in a 16x16mm 320 to 360 pin 0.8mm
  14 FBGA package.  Instead of single-issue higher clock rate, the design is
  15 multi-issue, aiming for around 800mhz.
  16
  17 The lower pincount, lower power, and higher BGA pitch is all to reduce
  18 the cost of product development when it comes to PCB design and layout:
  19
  20 * Above 4 watts requires metal packages, greater attention to thermal
  21   management in the PCB design and layout, and much pricier PMICs.
  22 * 0.6mm pitch BGA and below requires much more expensive PCB manufacturing
  23   equipment and more costly PCBA techniques.
  24 * Above 600 pins begins to reduce production yields as well as increase
  25   the cost of testing and packaging.
  26
  27 We can look at larger higher-power ASICs either later or, if funding
  28 is made available, immediately.
  29
  30 Recent applications to NLNet (Oct 2019) are for a test chip in 180nm, 64 bit, single core dual issue, around 300 to 350mhz.  This will provide the confidence to go to higher geometries, as well as be a commercially viable embedded product in its own right.
  31
  32 # Business Objectives
  33
  34 * the project shall be a hybrid CPU-GPU because if it is not, the
  35   complexity involved in developing a split shared-memory CPU-GPU both
  36   at a hardware and a software level will be so costly it will jeapordise
  37   the project.
  38 * the project shall be commercial and mass-volume (100 million units
  39   and above)
  40 * the project shall be entirely transparent so that end-users will be
  41   able to trust it
  42 * the source code shall be available at all times for all components
  43   for BUSINESS reasons, making development and use of SDKs dead simple
  44   and aiding and assisting developers AND BUSINESSES in debugging and thus
  45   hugely saving them money.
  46
  47 # Links:
  48
  49 * [[shakti/m_class/libre_3d_gpu]]
  50 * [[discussion]]
  51 * [[resources]]
  52 * [[overview]]
  53 * [[3d_gpu/funding]]
  54 * [[3d_gpu/architecture]]
  55 * Founding [[charter]]
  56 * Mailing list <http://lists.libre-riscv.org/pipermail/libre-riscv-dev/>
  57 * Crowdsupply page <https://www.crowdsupply.com/libre-risc-v/m-class>
  58 * Wiki <https://libre-riscv.org>
  59 * Git repositories <https://git.libre-riscv.org>
  60 * Bugtracker <http://bugs.libre-riscv.org>
  61 * Kazan Vulkan Driver (including 3D engine) <https://salsa.debian.org/Kazan-team/kazan>
  62 * [NLNet 2019 Milestones](http://bugs.libre-riscv.org/buglist.cgi?columnlist=assigned_to%2Cbug_status%2Cresolution%2Cshort_desc%2Ccf_budget&f1=cf_nlnet_milestone&o1=equals&query_format=advanced&resolution=---&v1=NLnet.2019.02)
  63 * NLNet Project Page <https://nlnet.nl/project/Libre-RISCV/>
  64 * [[nlnet_proposals]]
  65
  66 # Progress:
  67
  68 * Dec 2019: Second round NLNet questions answered.  External Review completed.  6 NLNet proposals accepted (EUR 200,000+)
  69 * Nov 2019: Alternative FP library to Berkeley softfloat developed. NLNet first round questions answered.
  70 * Oct 2019: 3D Standards continued.  POWER ISA considered.  Open 3D Alliance begins.  NLNet funding applications submitted.
  71 * Sep 2019: 3D Standards continued.  Additional NLNet Funding proposals discussed.
  72 * Aug 2019: Development of "Transcendentals" (SIN/COS/ATAN2) Specifications
  73 * Jul 2019: Sponsorship from Purism received.  IEEE754 FP Mul, Add, DIV,
  74   FCLASS and FCVT pipelines completed.
  75 * Jun 2019: IEEE754 FP Mul, Add, and FSM "DIV" completed.
  76 * May 2019: 6600-style scoreboard started
  77 * Apr 2019: NLnet funding approved by independent review committee
  78 * Mar 2019: NLnet funding application first and second phase passed
  79 * Mar 2019: First successful nmigen pipeline milestone achieved with IEEE754 FADD
  80 * Feb 2019: Conversion of John Dawson's IEEE754 FPU to nmigen started
  81 * Jan 2019: Second version Simple-V preliminary proposal (suited to LLVM)
  82 * 2017 - Nov 2018: Simple-V specification preliminary draft completed
  83 * Aug 2018 - Nov 2018: spike-sv implementation of draft spec completed
  84 * Aug 2018: Kazan Vulkan Driver initiated
  85 * Sep 2018: mailing list established
  86 * Sep 2018: Crowdsupply pre-launch page up (for updates)
  87 * Dec 2018: preliminary floorplan and architecture designed (comp.arch)
  88
  89 # News Articles
  90
  91 * <https://www.phoronix.com/forums/forum/hardware/processors-memory/1133806-libre-risc-v-open-source-effort-now-looking-at-power-instead-of-risc-v/page7>
  92 * <https://hub.packtpub.com/a-libre-gpu-effort-based-on-risc-v-rust-llvm-and-vulkan-by-the-developer-of-an-earth-friendly-computer/>
  93 * <https://riscv.org/2018/10/packt-hub-article-a-libre-gpu-effort-based-on-risc-v-rust-llvm-and-vulkan-by-the-developer-of-an-earth-friendly-computer/>
  94 * <https://www.reddit.com/r/RISCV/comments/9jts9t/theres_a_new_libre_gpu_effort_building_on_riscv/>
  95 * <https://www.linux.com/blog/2018/11/risc-v-linux-development-full-swing>
  96 * <https://www.phoronix.com/scan.php?page=news_item&px=Libre-GPU-RISC-V-Vulkan>
  97 * <https://www.heise.de/newsticker/meldung/Mobilprozessor-mit-freier-GPU-Libre-RISC-V-M-Class-geplant-4242802.html>
  98 * <https://news.ycombinator.com/item?id=18094734>
  99 * <http://www.tuxmachines.org/node/116004>
 100 * <https://linuxfr.org/users/martoni/journaux/risc-v-est-pret-pour-le-desktop>
 101 * <https://www.reddit.com/r/hardware/comments/9jlby1/theres_a_new_libre_gpu_effort_building_on_riscv/>
 102 * <http://www.eevblog.com/forum/crowd-funded-projects/libre-risc-v-m-class-with-open-source-gpu-and-kazan-vulkan-driver/>
 103 * <https://www.reddit.com/domain/libre-riscv.org/>
 104 * <https://hardware.slashdot.org/comments.pl?sid=13447940&cid=58160868>
 105 * <https://www.phoronix.com/forums/forum/hardware/graphics-cards/1080755-libre-risc-v-gpu-aiming-for-2-5-watt-power-draw-continues-being-plotted/page5>
 106 * <https://www.phoronix.com/forums/forum/hardware/processors-memory/1070828-more-details-on-the-proposed-simple-v-extension-to-risc-v-for-gpu-workloads>
 107 * <https://slashdot.org/submission/9750302/nlnet-funds-development-of-a-libre-risc-v-3d-cpu>
 108 * <https://hardware.slashdot.org/story/19/06/02/0153243/nlnet-funds-development-of-a-libre-risc-v-3d-cpu>
 109 * <https://www.phoronix.com/forums/forum/hardware/graphics-cards/1104124-libre-risc-v-snags-50k-eur-grant-to-work-on-its-risc-v-3d-gpu-chip/page6>
 110 * <https://news.ycombinator.com/item?id=21112341>
 111 * <https://www.reddit.com/r/RISCV/comments/db04j3/libreriscv_3d_cpugpu_seeks_grants_for_ambitious/>
 112 * <https://hardware.slashdot.org/story/19/09/29/1845252/libre-risc-v-3d-cpugpu-seeks-grants-for-ambitious-expansion>
 113 * <https://forums.puri.sm/t/risc-v-m-class-effort-and-purism-donation/6528/15>
 114 * <https://www.pro-linux.de/news/1/27527/comm/1/show-all-comments.html>
 115
 116 # Information Resources and Tutorials
 117
 118 * <https://github.com/timvideos/litex-buildenv/wiki/LiteX-for-Hardware-Engineers>
 119 * <https://jeffrey.co.in/blog/2014/01/d-flip-flop-using-migen/>
 120 * <http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2019-March/000705.html>
 121 * <https://chisel.eecs.berkeley.edu/api/latest/chisel3/util/DecoupledIO.html>
 122 * <http://www.clifford.at/papers/2016/yosys-synth-formal/slides.pdf>
 123 * <http://blog.lambdaconcept.com/doku.php?id=migen:tutorial>
 124 * <http://chiselapp.com/user/kc5tja/repository/kestrel-3/dir?ci=6c559135a301f321&name=cores/cpu>
 125 * <https://chips4makers.io/blog/>
 126 * <https://hackaday.io/project/7817-zynqberry>
 127 * <https://wiki.f-si.org/index.php/FSiC2019>
 128 * <https://github.com/efabless/raven-picorv32> - <https://efabless.com>
 129 * <https://efabless.com/design_catalog/default>
 130 * <https://toyota-ai.ventures/>
 131 * <https://github.com/lambdaconcept/minerva>
 132 * <https://en.wikipedia.org/wiki/Liskov_substitution_principle>
 133 * <https://en.wikipedia.org/wiki/Principle_of_least_astonishment>
 134 * <https://peertube.f-si.org/videos/watch/379ef007-40b7-4a51-ba1a-0db4f48e8b16>
 135 * <https://github.com/riscv/riscv-sbi-doc/blob/master/riscv-sbi.md>
 136 * <https://mshahrad.github.io/openpiton-asplos16.html>
 137 * <https://wiki.f-si.org/index.php/The_Raven_chip:_First-time_silicon_success_with_qflow_and_efabless>
 138 * <http://smallcultfollowing.com/babysteps/blog/2019/04/19/aic-adventures-in-consensus/>
 139 * <http://www.crnhq.org/12-Skills-Summary.aspx?rw=c>
 140 * <http://bugs.libre-riscv.org/buglist.cgi?columnlist=assigned_to%2Cbug_status%2Cresolution%2Cshort_desc%2Ccf_budget&f1=cf_nlnet_milestone&o1=equals&query_format=advanced&resolution=---&v1=NLnet.2019.02>
 141 * <https://pdfs.semanticscholar.org/5060/4e9aff0e37089c4ab9a376c3f35761ffe28b.pdf>
 142 * <http://www.acsel-lab.com/arithmetic/arith15/papers/ARITH15_Takagi.pdf>
 143 * <https://youtu.be/o5Ihqg72T3c>
 144 * <http://flopoco.gforge.inria.fr/>
 145 * Fundamentals of Modern VLSI Devices <https://groups.google.com/a/groups.riscv.org/d/msg/hw-dev/b4pPvlzBzu0/7hDfxArEAgAJ>
 146
 147 # Analog Simulation
 148
 149 * <https://github.com/Isotel/mixedsim>
 150 * <http://www.vlsiacademy.org/open-source-cad-tools.html>
 151 * <http://ngspice.sourceforge.net/adms.html>
 152 * <https://en.wikipedia.org/wiki/Verilog-AMS#Open_Source_Implementations>
 153
 154 # Evaluations
 155
 156 *[[openpower]]