3d_gpu.mdwn

   1 # RISC-V 3D GPU / CPU / VPU
   2
   3 Note: this is a **hybrid** CPU, VPU and GPU.  It is not, as many news articles
   4 are implying, a "dedicated exclusive GPU".  The option exists to **create**
   5 a stand-alone GPU product (contact us if this is a product that you want).
   6 Our primary goal is to design a **complete** all-in-one processor
   7 (System-on-a-Chip) that happens to include a libre-licensed VPU and GPU.
   8
   9 We seek investors, sponsors, engineers and potential customers, who are
  10 interested, as a first product, in the creation and use of an entirely
  11 libre low-power mobile class system-on-a-chip.  Comparative benchmark
  12 performance, pincount and price is the Allwinner A64, except that the
  13 power budget target is 2.5 watts in a 16x16mm 320 to 360 pin 0.8mm
  14 FBGA package.  Instead of single-issue higher clock rate, the design is
  15 multi-issue, aiming for around 800mhz.
  16
  17 The lower pincount, lower power, and higher BGA pitch is all to reduce
  18 the cost of product development when it comes to PCB design and layout:
  19
  20 * Above 4 watts requires metal packages, greater attention to thermal
  21   management in the PCB design and layout, and much pricier PMICs.
  22 * 0.6mm pitch BGA and below requires much more expensive PCB manufacturing
  23   equipment and more costly PCBA techniques.
  24 * Above 600 pins begins to reduce production yields as well as increase
  25   the cost of testing and packaging.
  26
  27 We can look at larger higher-power ASICs either later or, if funding
  28 is made available, immediately.
  29
  30 Recent applications (Oct 2019) are for a test chip in 180nm, 64 bit, single core dual issue, around 300 to 350mhz.  This will provide the confidence to go to higher geometries, as well as be a commercially viable embedded product in its own right.
  31
  32 See:
  33
  34 * [[shakti/m_class/libre_3d_gpu]]
  35 * [[discussion]]
  36 * [[resources]]
  37 * Founding [[charter]]
  38 * Mailing list <http://lists.libre-riscv.org/pipermail/libre-riscv-dev/>
  39 * Crowdsupply page <https://www.crowdsupply.com/libre-risc-v/m-class>
  40 * Wiki <https://libre-riscv.org>
  41 * Git repositories <https://git.libre-riscv.org>
  42 * Bugtracker <http://bugs.libre-riscv.org>
  43 * Kazan Vulkan Driver (including 3D engine) <https://salsa.debian.org/Kazan-team/kazan>
  44 * [NLNet 2019 Milestones](http://bugs.libre-riscv.org/buglist.cgi?columnlist=assigned_to%2Cbug_status%2Cresolution%2Cshort_desc%2Ccf_budget&f1=cf_nlnet_milestone&o1=equals&query_format=advanced&resolution=---&v1=NLnet.2019.02)
  45 * NLNet Project Page <https://nlnet.nl/project/Libre-RISCV/>
  46 * [[nlnet_proposals]]
  47
  48 Progress:
  49
  50 * Jul 2019: Sponsorship from Purism received.  IEEE754 FP Mul, Add, DIV,
  51   FCLASS and FCVT pipelines completed.
  52 * Jun 2019: IEEE754 FP Mul, Add, and FSM "DIV" completed.
  53 * May 2019: 6600-style scoreboard started
  54 * Apr 2019: NLnet funding approved by independent review committee
  55 * Mar 2019: NLnet funding application first and second phase passed
  56 * Mar 2019: First successful nmigen pipeline milestone achieved with IEEE754 FADD
  57 * Feb 2019: Conversion of John Dawson's IEEE754 FPU to nmigen started
  58 * Jan 2019: Second version Simple-V preliminary proposal (suited to LLVM)
  59 * 2017 - Nov 2018: Simple-V specification preliminary draft completed
  60 * Aug 2018 - Nov 2018: spike-sv implementation of draft spec completed
  61 * Aug 2018: Kazan Vulkan Driver initiated
  62 * Sep 2018: mailing list established
  63 * Sep 2018: Crowdsupply pre-launch page up (for updates)
  64 * Dec 2018: preliminary floorplan and architecture designed (comp.arch)
  65
  66 # News Articles
  67
  68 * <https://hub.packtpub.com/a-libre-gpu-effort-based-on-risc-v-rust-llvm-and-vulkan-by-the-developer-of-an-earth-friendly-computer/>
  69 * <https://riscv.org/2018/10/packt-hub-article-a-libre-gpu-effort-based-on-risc-v-rust-llvm-and-vulkan-by-the-developer-of-an-earth-friendly-computer/>
  70 * <https://www.reddit.com/r/RISCV/comments/9jts9t/theres_a_new_libre_gpu_effort_building_on_riscv/>
  71 * <https://www.linux.com/blog/2018/11/risc-v-linux-development-full-swing>
  72 * <https://www.phoronix.com/scan.php?page=news_item&px=Libre-GPU-RISC-V-Vulkan>
  73 * <https://www.heise.de/newsticker/meldung/Mobilprozessor-mit-freier-GPU-Libre-RISC-V-M-Class-geplant-4242802.html>
  74 * <https://news.ycombinator.com/item?id=18094734>
  75 * <http://www.tuxmachines.org/node/116004>
  76 * <https://linuxfr.org/users/martoni/journaux/risc-v-est-pret-pour-le-desktop>
  77 * <https://www.reddit.com/r/hardware/comments/9jlby1/theres_a_new_libre_gpu_effort_building_on_riscv/>
  78 * <http://www.eevblog.com/forum/crowd-funded-projects/libre-risc-v-m-class-with-open-source-gpu-and-kazan-vulkan-driver/>
  79 * <https://www.reddit.com/domain/libre-riscv.org/>
  80 * <https://hardware.slashdot.org/comments.pl?sid=13447940&cid=58160868>
  81 * <https://www.phoronix.com/forums/forum/hardware/graphics-cards/1080755-libre-risc-v-gpu-aiming-for-2-5-watt-power-draw-continues-being-plotted/page5>
  82 * <https://www.phoronix.com/forums/forum/hardware/processors-memory/1070828-more-details-on-the-proposed-simple-v-extension-to-risc-v-for-gpu-workloads>
  83 * <https://slashdot.org/submission/9750302/nlnet-funds-development-of-a-libre-risc-v-3d-cpu>
  84 * <https://hardware.slashdot.org/story/19/06/02/0153243/nlnet-funds-development-of-a-libre-risc-v-3d-cpu>
  85 * <https://www.phoronix.com/forums/forum/hardware/graphics-cards/1104124-libre-risc-v-snags-50k-eur-grant-to-work-on-its-risc-v-3d-gpu-chip/page6>
  86 * <https://news.ycombinator.com/item?id=21112341>
  87 * <https://www.reddit.com/r/RISCV/comments/db04j3/libreriscv_3d_cpugpu_seeks_grants_for_ambitious/>
  88 * <https://hardware.slashdot.org/story/19/09/29/1845252/libre-risc-v-3d-cpugpu-seeks-grants-for-ambitious-expansion>
  89 * <https://forums.puri.sm/t/risc-v-m-class-effort-and-purism-donation/6528/15>
  90
  91 # Information Resources and Tutorials
  92
  93 * <https://github.com/timvideos/litex-buildenv/wiki/LiteX-for-Hardware-Engineers>
  94 * <https://jeffrey.co.in/blog/2014/01/d-flip-flop-using-migen/>
  95 * <http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2019-March/000705.html>
  96 * <https://chisel.eecs.berkeley.edu/api/latest/chisel3/util/DecoupledIO.html>
  97 * <http://www.clifford.at/papers/2016/yosys-synth-formal/slides.pdf>
  98 * <http://blog.lambdaconcept.com/doku.php?id=migen:tutorial>
  99 * <http://chiselapp.com/user/kc5tja/repository/kestrel-3/dir?ci=6c559135a301f321&name=cores/cpu>
 100 * <https://chips4makers.io/blog/>
 101 * <https://hackaday.io/project/7817-zynqberry>
 102 * <https://wiki.f-si.org/index.php/FSiC2019>
 103 * <https://github.com/efabless/raven-picorv32> - <https://efabless.com>
 104 * <https://efabless.com/design_catalog/default>
 105 * <https://toyota-ai.ventures/>
 106 * <https://github.com/lambdaconcept/minerva>
 107 * <https://en.wikipedia.org/wiki/Liskov_substitution_principle>
 108 * <https://en.wikipedia.org/wiki/Principle_of_least_astonishment>
 109 * <https://peertube.f-si.org/videos/watch/379ef007-40b7-4a51-ba1a-0db4f48e8b16>
 110 * <https://github.com/riscv/riscv-sbi-doc/blob/master/riscv-sbi.md>
 111 * <https://mshahrad.github.io/openpiton-asplos16.html>
 112 * <https://wiki.f-si.org/index.php/The_Raven_chip:_First-time_silicon_success_with_qflow_and_efabless>
 113 * <http://smallcultfollowing.com/babysteps/blog/2019/04/19/aic-adventures-in-consensus/>
 114 * <http://www.crnhq.org/12-Skills-Summary.aspx?rw=c>
 115 * <http://bugs.libre-riscv.org/buglist.cgi?columnlist=assigned_to%2Cbug_status%2Cresolution%2Cshort_desc%2Ccf_budget&f1=cf_nlnet_milestone&o1=equals&query_format=advanced&resolution=---&v1=NLnet.2019.02>
 116 * <https://pdfs.semanticscholar.org/5060/4e9aff0e37089c4ab9a376c3f35761ffe28b.pdf>
 117 * <http://www.acsel-lab.com/arithmetic/arith15/papers/ARITH15_Takagi.pdf>
 118 * <https://youtu.be/o5Ihqg72T3c>
 119 * <http://flopoco.gforge.inria.fr/>
 120 * Fundamentals of Modern VLSI Devices <https://groups.google.com/a/groups.riscv.org/d/msg/hw-dev/b4pPvlzBzu0/7hDfxArEAgAJ>
 121
 122 # Analog Simulation
 123
 124 * <https://github.com/Isotel/mixedsim>
 125 * <http://www.vlsiacademy.org/open-source-cad-tools.html>
 126 * <http://ngspice.sourceforge.net/adms.html>
 127 * <https://en.wikipedia.org/wiki/Verilog-AMS#Open_Source_Implementations>