3d_gpu.mdwn

   1 See architectural details [here](./architecture)
   2
   3 # "Gaddie Pitch" (1) for LibreSOC
   4
   5 | What we do               | Benefits              | Feelings                |
   6 | ------------------------ | --------------------- | ----------------------- |
   7 | design high-performance  | No spying backdoors,  | Much less frustrated    |
   8 | efficient and simpler    | greatly reduced time  | when developing products|
   9 | processors with built-in | and cost to market    | using e.g. China-based  |
  10 | 3D and Video capability  | Simpler debugging     | products.  End-customer |
  11 | in a fully-transparent   | Full transparency     | stops complaining,      |
  12 | fashion.                 | for their customers   | Risk and worry gone.    |
  13
  14 ## You know how...
  15
  16 You know how for computers, you really have no idea how they work? And
  17 how you keep having to replace them with upgrades?  Turns out that
  18 it's very difficult for medium-sized businesses to design lower-cost products
  19 because the only cheap processors (almost always from China) do not respect
  20 Copyright law, provide almost zero documentation, and even Intel processors
  21 are known to have spying backdoor co-processors in them?
  22
  23 ## Well what we do is...
  24
  25 Well, what we do is: design 3D-capable efficient processors based on
  26 full transparency.  All source code, right to the bedrock, hardware
  27 and software.  We don't tell customers "trust us", we say "go have a
  28 specialist audit the full source, independently".  If there's ever
  29 some documentation missing, the customer can check for themselves when
  30 designing *their* product around ours.
  31
  32 ## In fact...
  33
  34 In fact, one customer that we're talking to is so fed up with a Chinese-based
  35 $35 component that they are using in a $3000 product, where they are having
  36 to spend considerable resources to *reverse-engineer* the China component,
  37 they are so fed up that they're willing to bet on our product even before we've
  38 completed it, they believe in the approach and our design that much.
  39
  40 # "Gaddie Pitch" (2) for LibreSOC
  41
  42 Cole TODO
  43
  44 # Hybrid 3D GPU / CPU / VPU
  45
  46 Creating a trustworthy processor for the world.
  47
  48 Our [[3d_gpu/business_objectives]]
  49
  50 Note: this is a **hybrid** CPU, VPU and GPU.  It is not, as many news articles
  51 are implying, a "dedicated exclusive GPU".  The option exists to *create*
  52 a stand-alone GPU product (contact us if this is a product that you want).
  53 Our primary goal is to design a **complete** all-in-one processor
  54 (System-on-a-Chip) that happens to include libre-licensed VPU and GPU
  55 accelerated instructions as part of the actual - main - CPU itself.  This greatly simplifies driver development, applications integration and debugging, reducing costs and time to market in the process.
  56
  57 We seek investors, sponsors (whose contributions thanks to NLNet may be
  58 tax-deductible), engineers and potential customers, who are
  59 interested, as a first product, in the creation and use of an entirely
  60 libre low-power mobile class system-on-a-chip
  61 [[shakti/m_class/]].  Comparative benchmark
  62 performance, pincount and price is the Allwinner A64, except that the
  63 power budget target is 2.5 watts in a 16x16mm 320 to 360 pin 0.8mm
  64 FBGA package.  Instead of single-issue higher clock rate, the design is
  65 multi-issue, aiming for around 800mhz.
  66
  67 The lower pincount, lower power, and higher BGA pitch is all to reduce
  68 the cost of product development when it comes to PCB design and layout:
  69
  70 * Above 4 watts requires metal packages, greater attention to thermal
  71   management in the PCB design and layout, and much pricier PMICs.
  72 * 0.6mm pitch BGA and below requires much more expensive PCB manufacturing
  73   equipment and more costly PCBA techniques.
  74 * Above 600 pins begins to reduce production yields as well as increase
  75   the cost of testing and packaging.
  76
  77 We can look at larger higher-power ASICs either later or, if funding
  78 is made available, immediately.
  79
  80 Recent applications to NLNet (Oct 2019) are for a test chip in 180nm,
  81 64 bit, single core dual issue, around 300 to 350mhz.  This will provide
  82 the confidence to go to higher geometries, as well as be a commercially
  83 viable embedded product in its own right. Tapeout deadline is Oct 2020.
  84
  85 See [[3d_gpu/articles]] online.
  86
  87 # Progress:
  88
  89 * Oct 2020 [[180nm_Oct2020/ls180/]] pinouts decided, code-freeze initiated
  90   for 180nm test ASIC, GDSII deadline set of Dec 2nd.
  91 * Sep 2020: [first boot](https://youtu.be/72QmWro9BSE) of Litex BIOS on a Versa ECP5 at 55mhz.  DDR3 RAM initialisation successful. 180nm ASIC pinouts started [[180nm_Oct2020/ls180]]
  92 * Aug 2020: [first boot](https://libre-soc.org/3d_gpu/libresoc_litex_bios_first_execution_2020-08-06_16-15.png) of litex BIOS in verilator simulation
  93 * Jul 2020: first ppc64le "hello world" binary executed.  80,000 gate coriolis2 auto-layout completed with 99.98% routing. Wishbone MoU signed making available access to an additional EUR 50,000 donations from NLNet. XDC2020 and OpenPOWER conference submissions entered.
  94 * Jun 2020: core unit tests and pipeline formal correctness proofs in place.
  95 * May 2020: first integer pipelines (ALU, Logical, Branch, Trap, SPR, ShiftRot, Mul, Div) and register files (XER, CR, INT, FAST, SPR) started.
  96 * Mar 2020: Coriolis2 Layout experiments successful. 6600 Memory Architecture
  97   exploration started.  OpenPOWER ISA decoder started.  Two new people:
  98   Alain and Jock.
  99 * Feb 2020: OpenPower Foundation EULA released. Coriolis2 Layout experimentation begun. Dynamic Partitioned SIMD ALU created.
 100 * Jan 2020: New team members, Yehowshua and Michael.  Last-minute attendance of FOSDEM2020
 101 * Dec 2019: Second round NLNet questions answered.  External Review completed.  6 NLNet proposals accepted (EUR 200,000+)
 102 * Nov 2019: Alternative FP library to Berkeley softfloat developed. NLNet first round questions answered.
 103 * Oct 2019: 3D Standards continued.  POWER ISA considered.  Open 3D Alliance begins.  NLNet funding applications submitted.
 104 * Sep 2019: 3D Standards continued.  Additional NLNet Funding proposals discussed.
 105 * Aug 2019: Development of "Transcendentals" (SIN/COS/ATAN2) Specifications
 106 * Jul 2019: Sponsorship from Purism received.  IEEE754 FP Mul, Add, DIV,
 107   FCLASS and FCVT pipelines completed.
 108 * Jun 2019: IEEE754 FP Mul, Add, and FSM "DIV" completed.
 109 * May 2019: 6600-style scoreboard started
 110 * Apr 2019: NLnet funding approved by independent review committee
 111 * Mar 2019: NLnet funding application first and second phase passed
 112 * Mar 2019: First successful nmigen pipeline milestone achieved with IEEE754 FADD
 113 * Feb 2019: Conversion of John Dawson's IEEE754 FPU to nmigen started
 114 * Jan 2019: Second version Simple-V preliminary proposal (suited to LLVM)
 115 * 2017 - Nov 2018: Simple-V specification preliminary draft completed
 116 * Aug 2018 - Nov 2018: spike-sv implementation of draft spec completed
 117 * Aug 2018: Kazan Vulkan Driver initiated
 118 * Sep 2018: mailing list established
 119 * Sep 2018: Crowdsupply pre-launch page up (for updates)
 120 * Dec 2018: preliminary floorplan and architecture designed (comp.arch)
 121
 122
 123 # Evaluations
 124
 125 * [[openpower]]
 126
 127 # Drivers
 128
 129 * [[3d_gpu/opencl]]
 130 * [[3d_gpu/mesa]]