Cesar_Strauss.mdwn

   1 # Cesar Strauss
   2
   3 Contributor
   4
   5 * [Bugtracker assignments](https://bugs.libre-soc.org/buglist.cgi?email1=cestrauss@gmail.com&emailassigned_to1=1&emailcc1=1&emailtype1=substring&resolution=---)
   6
   7 # Status Tracking
   8
   9 ## Currently working on
  10
  11 1. ALU CompUnit needs to recognise that RA (src1) can be zero
  12         <https://bugs.libre-soc.org/show_bug.cgi?id=336>
  13         Status: DONE
  14         Unit test Status: in progress
  15
  16
  17 2. Something about the above (5), being optional.
  18         <https://bugs.libre-soc.org/show_bug.cgi?id=336#c5>
  19         Status: DONE
  20         Unit test Status: in progress
  21
  22 3. CompALUMulti parallel functions unit test
  23         <https://bugs.libre-soc.org/show_bug.cgi?id=336#c11>
  24         Priority: Medium-to-High
  25
  26 4. Code-morph LDSTCompUnit to use RecordObject structure, like CompUnitALU
  27         <https://bugs.libre-soc.org/show_bug.cgi?id=318#c18>
  28         Status: Need a review of Luke's implementation, compared to mine.
  29         Priority: Low
  30
  31 5. Test dual ports (two L0CacheBuffer with two ports, 4-4 as well) which
  32 write to the same memory
  33         <https://bugs.libre-soc.org/show_bug.cgi?id=318#c11>
  34         Status: not started
  35         Priority: High
  36
  37 6. Luke tried two LDs in the score6600 code - they failed.
  38         <https://bugs.libre-soc.org/show_bug.cgi?id=318#c17>
  39         Status: not started, need to check the [prototype] L0CacheBuffer
  40         Priority: High
  41
  42 7. Fix a bug in the LDSTCompUnit
  43         <https://bugs.libre-soc.org/show_bug.cgi?id=318>
  44         Status: Luke thinks he fixed it, but needs a review and improving the
  45 unit tests.
  46         See: <https://bugs.libre-soc.org/show_bug.cgi?id=318#c7>
  47         Priority: Medium
  48
  49 8. LDSTCompUnit parallel functions unit test
  50         <https://bugs.libre-soc.org/show_bug.cgi?id=350>
  51         Priority: Medium-ish
  52
  53 11. Formal Proof for CompUnit
  54         <https://bugs.libre-soc.org/show_bug.cgi?id=342>
  55
  56 12. Formal Proof for PartitionedSignal
  57         <https://bugs.libre-soc.org/show_bug.cgi?id=565>
  58         Status: in progress
  59
  60 13. Implement simple VL for-loop in nMigen for TestIssuer
  61         <https://bugs.libre-soc.org/show_bug.cgi?id=583>
  62         Status: in progress
  63
  64 ## Completed but not yet submitted:
  65
  66 1. FSM-based ALU example needed (compliant with ALU CompUnit)
  67         <https://bugs.libre-soc.org/show_bug.cgi?id=417>
  68
  69 2. Fix MSB0 issues in the SVP64 Assembler, Simulator and Decoder
  70         <https://bugs.libre-soc.org/show_bug.cgi?id=600>
  71
  72 ## Submitted for NLNet RFP
  73
  74 ### NLnet.2019.02.012
  75
  76 * [Bug #583](https://bugs.libre-soc.org/show_bug.cgi?id=583):
  77   Implement simple VL for\-loop in nMigen for TestIssuer
  78     * &euro;2325 which is the total amount
  79     * submitted on 2022-06-16
  80
  81 ### NLNet.2019.10.032.Formal
  82
  83 * [Bug #565](https://bugs.libre-soc.org/show_bug.cgi?id=565):
  84   Improve formal verification on PartitionedSignal
  85     * &euro;2200 out of total of &euro;3000
  86     * submitted on 2022-06-16
  87
  88 ### NLNet.2019.10.046.Standards
  89
  90 * [Bug #588](https://bugs.libre-soc.org/show_bug.cgi?id=588):
  91   add SVP64 to PowerDecoder2
  92     * &euro;300 out of total of &euro;1000
  93     * submitted on 2022-06-16
  94
  95 ## Paid
  96
  97 ### NLNet.2019.10.043.Wishbone
  98
  99 * [Bug #475](https://bugs.libre-soc.org/show_bug.cgi?id=475):
 100   cxxsim improvements
 101     * Ran several Libre-SOC tests under cxxsim
 102     * Helped isolate simulator issues by extracting a MVCE
 103 (Minimal, Verifiable, Complete Example) in each case.
 104     * paid on 2021-05-11
 105     * &euro;250 out of total of &euro;1750