alt_rvp.mdwn

   1 # Lanes
   2
   3 The term "Lanes" is borrowed from Hwacha.
   4
   5 Register table
   6
   7 | reg num | Lane 0 | Lane 1 | Lane 2 | Lane 3 |
   8 | ------- | ------ | ------ | ------ | ------ |
   9 | r0      | (31.0) | (31.0) | (31.0) | (31.0) |
  10 | r1      | (31.0) | (31.0) | (31.0) | (31.0) |
  11 | r2      | (31.0) | (31.0) | (31.0) | (31.0) |
  12
  13 Example parallel add:
  14
  15     /* XLEN and N are "baked-in" to the hardware */
  16     parameter XLEN;
  17     parameter N;
  18     /* note that N cannot be greater than XLEN */
  19
  20     register plane[XLEN];
  21     register x[N][32][XLEN];
  22
  23     function op_add(rd, rs1, rs2) {
  24        /* note that this is ADD, not PADD */
  25        int i;
  26        for (i = 0; i<N; i++)
  27           if (plane[i])
  28              x[i][rd] <= x[i][rs1] + x[i][rs2];
  29     }
  30     /* note that "<=" is the Verilog non-blocking assignment operator */
  31